netdev - RE: [PATCH] ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnect

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <VI1PR04MB4880FE626BF9E898FD898495965E0@VI1PR04MB4880.eurprd04.prod.outlook.com>
Date:   Mon, 25 Mar 2019 15:26:03 +0000
From:   Claudiu Manoil <claudiu.manoil@....com>
To:     Vladimir Oltean <vladimir.oltean@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Leo Li <leoyang.li@....com>
CC:     "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "davem@...emloft.net" <davem@...emloft.net>
Subject: RE: [PATCH] ARM: dts: ls1021: Fix SGMII PCS link remaining down after
 PHY disconnect

>-----Original Message-----
>From: Vladimir Oltean
>Sent: Monday, March 25, 2019 11:31 AM
>To: shawnguo@...nel.org; Leo Li <leoyang.li@....com>; Claudiu Manoil
><claudiu.manoil@....com>
>Cc: robh+dt@...nel.org; linux-arm-kernel@...ts.infradead.org;
>devicetree@...r.kernel.org; linux-kernel@...r.kernel.org;
>netdev@...r.kernel.org; davem@...emloft.net; Vladimir Oltean
><vladimir.oltean@....com>
>Subject: [PATCH] ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY
>disconnect
>
>Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
>But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC are
>pointing towards the same internal PCS. Therefore nobody is controlling the
>internal PCS of eTSEC0.
>
>Upon initial ndo_open, the SGMII link is ok by virtue of U-boot initialization. But
>upon an ifdown/ifup sequence, the code path from ndo_open -> init_phy ->
>gfar_configure_serdes does not get executed for the PCS of eTSEC0 (and is
>executed twice for MAC eTSEC1). So the SGMII link remains down for eTSEC0.
>On the LS1021A-TWR board, to signal this failure condition, the PHY driver keeps
>printing
>'803x_aneg_done: SGMII link is not ok'.
>
>Fixes: 055223d4d22d ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and
>TWR")
>Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>

Reviewed-by: Claudiu Manoil <claudiu.manoil@....com>