netdev - RE: [PATCH 1/2] stmmac: introduce flag to dynamically disable TX offload for rockchip devices

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Date:   Fri, 5 Apr 2019 10:24:00 +0000
From:   Jose Abreu <jose.abreu@...opsys.com>
To:     Robin Murphy <robin.murphy@....com>,
        "Leonidas P. Papadakos" <papadakospan@...il.com>,
        Jose Abreu <jose.abreu@...opsys.com>
CC:     Philipp Tomsich <philipp.tomsich@...obroma-systems.com>,
        Heiko Stübner <heiko@...ech.de>,
        Christoph Müllner 
        <christoph.muellner@...obroma-systems.com>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Klaus Goger <klaus.goger@...obroma-systems.com>
Subject: RE: [PATCH 1/2] stmmac: introduce flag to dynamically disable TX
 offload for rockchip devices

From: Robin Murphy <robin.murphy@....com>
Date: Wed, Apr 03, 2019 at 17:12:03

> Yes, I would expect software checksumming to have a much more noticeable 
> impact (in fact I've already been trying to get round to benchmarking 
> some arm64 checksum optimisations on my RK3328 precisely because of this 
> issue).
> 

Can you share the optimizations ? 😊

> If I'm interpreting the register descriptions in the Rockchip TRMs 
> correctly, it seems like no-pbl-x8 is a relatively big hammer and there 
> should still be room to tune things a bit closer to the maximum limits - 
> I'll have another play this evening to see if I've understood things right.

You can play around different PBL values without using the no-pbl-x8 option.

I would start with PBL=0x1 and then going up. If PBL=0x1 does not work then
add the no-pbl-x8 option and start with PBL=0x20 and keep decreasing.

Thanks,
Jose Miguel Abreu