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Message-Id: <1556134382-58814-6-git-send-email-fenghua.yu@intel.com> Date: Wed, 24 Apr 2019 12:32:52 -0700 From: Fenghua Yu <fenghua.yu@...el.com> To: "Thomas Gleixner" <tglx@...utronix.de>, "Ingo Molnar" <mingo@...hat.com>, "Borislav Petkov" <bp@...en8.de>, "H Peter Anvin" <hpa@...or.com>, "Paolo Bonzini" <pbonzini@...hat.com>, "Dave Hansen" <dave.hansen@...el.com>, "Ashok Raj" <ashok.raj@...el.com>, "Peter Zijlstra" <peterz@...radead.org>, "Ravi V Shankar" <ravi.v.shankar@...el.com>, "Xiaoyao Li " <xiaoyao.li@...el.com>, "Christopherson Sean J" <sean.j.christopherson@...el.com>, "Kalle Valo" <kvalo@...eaurora.org>, "Michael Chan" <michael.chan@...adcom.com> Cc: "linux-kernel" <linux-kernel@...r.kernel.org>, "x86" <x86@...nel.org>, kvm@...r.kernel.org, netdev@...r.kernel.org, linux-wireless@...r.kernel.org, Fenghua Yu <fenghua.yu@...el.com> Subject: [PATCH v8 05/15] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY and split lock detection bit A new MSR_IA32_CORE_CAPABILITY (0xcf) is defined. Each bit in the MSR enumerates a model specific feature. Currently bit 5 enumerates split lock detection. When bit 5 is 1, split lock detection is supported. When the bit is 0, split lock detection is not supported. Please check the latest Intel 64 and IA-32 Architectures Software Developer's Manual for more detailed information on the MSR and the split lock detection bit. Signed-off-by: Fenghua Yu <fenghua.yu@...el.com> --- arch/x86/include/asm/msr-index.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ca5bc0eacb95..f65ef6f783d2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -59,6 +59,9 @@ #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) +#define MSR_IA32_CORE_CAPABILITY 0x000000cf +#define CORE_CAP_SPLIT_LOCK_DETECT BIT(5) /* Detect split lock */ + #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) -- 2.19.1
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