netdev - Re: [PATCH v8 05/15] x86/msr-index: Define MSR_IA32_CORE

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 26 Apr 2019 08:00:10 +0200
From:   Ingo Molnar <mingo@...nel.org>
To:     Fenghua Yu <fenghua.yu@...el.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        H Peter Anvin <hpa@...or.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Dave Hansen <dave.hansen@...el.com>,
        Ashok Raj <ashok.raj@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ravi V Shankar <ravi.v.shankar@...el.com>,
        Xiaoyao Li <xiaoyao.li@...el.com>,
        Christopherson Sean J <sean.j.christopherson@...el.com>,
        Kalle Valo <kvalo@...eaurora.org>,
        Michael Chan <michael.chan@...adcom.com>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        x86 <x86@...nel.org>, kvm@...r.kernel.org,
        netdev@...r.kernel.org, linux-wireless@...r.kernel.org
Subject: Re: [PATCH v8 05/15] x86/msr-index: Define MSR_IA32_CORE_CAPABILITY
 and split lock detection bit


* Fenghua Yu <fenghua.yu@...el.com> wrote:

> On Thu, Apr 25, 2019 at 10:08:30PM +0200, Ingo Molnar wrote:
> > 
> > * Fenghua Yu <fenghua.yu@...el.com> wrote:
> > 
> > > On Thu, Apr 25, 2019 at 09:47:14PM +0200, Ingo Molnar wrote:
> > > > 
> > > > * Fenghua Yu <fenghua.yu@...el.com> wrote:
> > > > 
> > > > > On Thu, Apr 25, 2019 at 07:45:11AM +0200, Ingo Molnar wrote:
> > > > > > 
> > > > > > * Fenghua Yu <fenghua.yu@...el.com> wrote:
> > > > > > 
> > > > > > > A new MSR_IA32_CORE_CAPABILITY (0xcf) is defined. Each bit in the MSR
> > > > > > > enumerates a model specific feature. Currently bit 5 enumerates split
> > > > > > > lock detection. When bit 5 is 1, split lock detection is supported.
> > > > > > > When the bit is 0, split lock detection is not supported.
> > > > > > > 
> > > > > > > Please check the latest Intel 64 and IA-32 Architectures Software
> > > > > > > Developer's Manual for more detailed information on the MSR and the
> > > > > > > split lock detection bit.
> > > > > > > 
> > > > > > > Signed-off-by: Fenghua Yu <fenghua.yu@...el.com>
> > > > > > > ---
> > > > > > >  arch/x86/include/asm/msr-index.h | 3 +++
> > > > > > >  1 file changed, 3 insertions(+)
> > > > > > > 
> > > > > > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> > > > > > > index ca5bc0eacb95..f65ef6f783d2 100644
> > > > > > > --- a/arch/x86/include/asm/msr-index.h
> > > > > > > +++ b/arch/x86/include/asm/msr-index.h
> > > > > > > @@ -59,6 +59,9 @@
> > > > > > >  #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31
> > > > > > >  #define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
> > > > > > >  
> > > > > > > +#define MSR_IA32_CORE_CAPABILITY	0x000000cf
> > > > > > > +#define CORE_CAP_SPLIT_LOCK_DETECT	BIT(5)     /* Detect split lock */
> > > > > > 
> > > > > > Please don't put comments into definitions.
> > > > > 
> > > > > I'll remove the comment and change definitions of the MSR and the split lock
> > > > > detection bit as following:
> > > > > 
> > > > > +#define MSR_IA32_CORE_CAPABILITY                       0x000000cf
> > > > > +#define MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT_BIT 5
> > > > > +#define MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT     BIT(MSR_IA32_CORE_CAPABILITY_SPLIT_LOCK_DETECT_BIT)
> > > > > 
> > > > > Are these right changes?
> > > > 
> > > > I suspect it could be shortened to CORE_CAP as you (partly) did it 
> > > > originally.
> > > 
> > > IA32_CORE_CAPABILITY is the MSR's exact name in the latest SDM (in Table 2-14):
> > > https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4
> > > 
> > > So can I define the MSR and the bits as follows?
> > > 
> > > +#define MSR_IA32_CORE_CAP                       0x000000cf
> > > +#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT 5
> > > +#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT     BIT(MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT)
> > 
> > Yeah, I suppose that looks OK.
> 
> Should I also change the feature definition 'X86_FEATURE_CORE_CAPABILITY' to
> 'X86_FEATURE_CORE_CAP' in cpufeatures.h in patch #0006 to match the
> MSR definition here? Or should I still keep the current feature definition?
> 
> Thanks.

Hm, no, for CPU features it's good to follow the vendor convention.

So I guess the long-form CPU_CAPABILITY for all of these is the best 
after all.

Thanks,

	Ingo