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Date: Sun, 28 Apr 2019 14:30:09 +0800 From: Biao Huang <biao.huang@...iatek.com> To: Jose Abreu <joabreu@...opsys.com>, <davem@...emloft.net> CC: Giuseppe Cavallaro <peppe.cavallaro@...com>, Alexandre Torgue <alexandre.torgue@...com>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Matthias Brugger <matthias.bgg@...il.com>, <netdev@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>, <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>, <yt.shen@...iatek.com>, <biao.huang@...iatek.com>, <jianguo.zhang@...iatek.com> Subject: [PATCH 6/6] stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail The frequency of csr clock is 66.5MHz, so the csr_clk value should be 0. Modify the csr_clk value to fix mdio read/write fail issue. Signed-off-by: Biao Huang <biao.huang@...iatek.com> --- .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index bf25629..6b12d0f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -346,8 +346,8 @@ static int mediatek_dwmac_probe(struct platform_device *pdev) return PTR_ERR(plat_dat); plat_dat->interface = priv_plat->phy_mode; - /* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */ - plat_dat->clk_csr = 5; + /* clk_csr_i = 60-100MHz & MDC = clk_csr_i/42 */ + plat_dat->clk_csr = 0; plat_dat->has_gmac4 = 1; plat_dat->has_gmac = 0; plat_dat->pmt = 0; -- 1.7.9.5
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