lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 29 Apr 2019 22:30:36 +0000
From:   Mark Bloch <markb@...lanox.com>
To:     Parav Pandit <parav@...lanox.com>,
        Leon Romanovsky <leonro@...lanox.com>,
        Saeed Mahameed <saeedm@...lanox.com>
CC:     Jason Gunthorpe <jgg@...lanox.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        Maor Gottlieb <maorg@...lanox.com>
Subject: Re: [PATCH V2 mlx5-next 09/11] net/mlx5: Eswitch, enable RoCE
 loopback traffic



On 4/29/19 11:45 AM, Parav Pandit wrote:
> 
> 
>> -----Original Message-----
>> From: netdev-owner@...r.kernel.org <netdev-owner@...r.kernel.org> On
>> Behalf Of Leon Romanovsky
>> Sent: Monday, April 29, 2019 1:41 PM
>> To: Saeed Mahameed <saeedm@...lanox.com>
>> Cc: Jason Gunthorpe <jgg@...lanox.com>; netdev@...r.kernel.org; linux-
>> rdma@...r.kernel.org; Maor Gottlieb <maorg@...lanox.com>; Mark Bloch
>> <markb@...lanox.com>
>> Subject: Re: [PATCH V2 mlx5-next 09/11] net/mlx5: Eswitch, enable RoCE
>> loopback traffic
>>
>> On Mon, Apr 29, 2019 at 06:14:16PM +0000, Saeed Mahameed wrote:
>>> From: Maor Gottlieb <maorg@...lanox.com>
>>>
>>> When in switchdev mode, we would like to treat loopback RoCE traffic
>>> (on eswitch manager) as RDMA and not as regular Ethernet traffic In
>>> order to enable it we add flow steering rule that forward RoCE
>>> loopback traffic to the HW RoCE filter (by adding allow rule).
>>> In addition we add RoCE address in GID index 0, which will be set in
>>> the RoCE loopback packet.
>>>
> I likely don't understand nor I reviewed the patches.
> Part that I don't understand is GID index 0 for RoCE.
> RoCE traffic runs over all the GID entries and for all practical purposes from non_zero index.
> How will it work?

Currently in switchdev mode we only support RAW Ethernet QP and no RoCE capabilities are reported to ib_core.
Which means no GIDs are inserted to the HW's GID table and RoCE isn't enabled on the vport.

However, there are cases where an internal RC QP might be needed, and for that we need a GID.
The patches from Maor make sure a GID entry at index 0 is valid (and we do that only in switchdev mode),
and with steering we make sure such traffic is only used for loopback purposes.

Mark
 
> It is better if you explain it in the commit log, why its done this way, 'what' part is already present the patch.
> 
> 
>>> Signed-off-by: Maor Gottlieb <maorg@...lanox.com>
>>> Reviewed-by: Mark Bloch <markb@...lanox.com>
>>> Signed-off-by: Saeed Mahameed <saeedm@...lanox.com>
>>> ---
>>>  .../net/ethernet/mellanox/mlx5/core/Makefile  |   2 +-
>>>  .../mellanox/mlx5/core/eswitch_offloads.c     |   4 +
>>>  .../net/ethernet/mellanox/mlx5/core/rdma.c    | 182 ++++++++++++++++++
>>>  .../net/ethernet/mellanox/mlx5/core/rdma.h    |  20 ++
>>>  include/linux/mlx5/driver.h                   |   7 +
>>>  5 files changed, 214 insertions(+), 1 deletion(-)  create mode 100644
>>> drivers/net/ethernet/mellanox/mlx5/core/rdma.c
>>>  create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/rdma.h
>>>
>>
>> Thanks,
>> Acked-by: Leon Romanovsky <leonro@...lanox.com>

Powered by blists - more mailing lists