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Message-Id: <1556721842-29836-13-git-send-email-jiong.wang@netronome.com> Date: Wed, 1 May 2019 15:43:57 +0100 From: Jiong Wang <jiong.wang@...ronome.com> To: alexei.starovoitov@...il.com, daniel@...earbox.net Cc: bpf@...r.kernel.org, netdev@...r.kernel.org, oss-drivers@...ronome.com, Jiong Wang <jiong.wang@...ronome.com>, "Naveen N . Rao" <naveen.n.rao@...ux.ibm.com>, Sandipan Das <sandipan@...ux.ibm.com> Subject: [PATCH v5 bpf-next 12/17] powerpc: bpf: eliminate zero extension code-gen Cc: Naveen N. Rao <naveen.n.rao@...ux.ibm.com> Cc: Sandipan Das <sandipan@...ux.ibm.com> Signed-off-by: Jiong Wang <jiong.wang@...ronome.com> --- arch/powerpc/net/bpf_jit_comp64.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c index 21a1dcd..2266c7c 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -557,9 +557,15 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, goto bpf_alu32_trunc; break; + /* + * ZEXT, does low 32-bit zero extension unconditionally + */ + case BPF_ALU | BPF_ZEXT: + PPC_RLWINM(dst_reg, dst_reg, 0, 0, 31); + break; bpf_alu32_trunc: /* Truncate to 32-bits */ - if (BPF_CLASS(code) == BPF_ALU) + if (BPF_CLASS(code) == BPF_ALU && !fp->aux->verifier_zext) PPC_RLWINM(dst_reg, dst_reg, 0, 0, 31); break; @@ -1046,6 +1052,11 @@ struct powerpc64_jit_data { struct codegen_context ctx; }; +bool bpf_jit_hardware_zext(void) +{ + return false; +} + struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp) { u32 proglen; -- 2.7.4
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