netdev - Re: [RFC PATCH 1/5] net: dsa: mv88e6xxx: introduce support for two chips using direct smi addressing

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Date:   Wed, 8 May 2019 07:57:38 +0000
From:   Rasmus Villemoes <rasmus.villemoes@...vas.dk>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vivien Didelot <vivien.didelot@...il.com>
Subject: Re: [RFC PATCH 1/5] net: dsa: mv88e6xxx: introduce support for two
 chips using direct smi addressing

On 01/05/2019 22.19, Andrew Lunn wrote:
> On Wed, May 01, 2019 at 07:32:10PM +0000, Rasmus Villemoes wrote:
>> The 88e6250 (as well as 6220, 6071, 6070, 6020) do not support
>> multi-chip (indirect) addressing. However, one can still have two of
>> them on the same mdio bus, since the device only uses 16 of the 32
>> possible addresses, either addresses 0x00-0x0F or 0x10-0x1F depending
>> on the ADDR4 pin at reset [since ADDR4 is internally pulled high, the
>> latter is the default].
>>
>> In order to prepare for supporting the 88e6250 and friends, introduce
>> mv88e6xxx_info::dual_chip to allow having a non-zero sw_addr while
>> still using direct addressing.
>>
>> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@...vas.dk>
>> ---
>>  drivers/net/dsa/mv88e6xxx/chip.c | 10 +++++++---
>>  drivers/net/dsa/mv88e6xxx/chip.h |  5 +++++
>>  2 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
>> index c078c791f481..f66daa77774b 100644
>> --- a/drivers/net/dsa/mv88e6xxx/chip.c
>> +++ b/drivers/net/dsa/mv88e6xxx/chip.c
>> @@ -62,6 +62,10 @@ static void assert_reg_lock(struct mv88e6xxx_chip *chip)
>>   * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
>>   * multiple devices to share the SMI interface. In this mode it responds to only
>>   * 2 registers, used to indirectly access the internal SMI devices.
>> + *
>> + * Some chips use a different scheme: Only the ADDR4 pin is used for
>> + * configuration, and the device responds to 16 of the 32 SMI
>> + * addresses, allowing two to coexist on the same SMI interface.
>>   */
>>  
>>  static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
>> @@ -87,7 +91,7 @@ static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
>>  {
>>  	int ret;
>>  
>> -	ret = mdiobus_read_nested(chip->bus, addr, reg);
>> +	ret = mdiobus_read_nested(chip->bus, addr + chip->sw_addr, reg);
>>  	if (ret < 0)
>>  		return ret;
>>  
>> @@ -101,7 +105,7 @@ static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
>>  {
>>  	int ret;
>>  
>> -	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
>> +	ret = mdiobus_write_nested(chip->bus, addr + chip->sw_addr, reg, val);
>>  	if (ret < 0)
>>  		return ret;
> 
> Hi Rasmus
> 
> This works, but i think i prefer adding mv88e6xxx_smi_dual_chip_write,
> mv88e6xxx_smi_dual_chip_read, and create a
> mv88e6xxx_smi_single_chip_ops.

Hi Andrew

Now that Vivien's "net: dsa: mv88e6xxx: refine SMI support" is in
master, do you still prefer introducing a third bus_ops structure
(mv88e6xxx_smi_dual_direct_ops ?), or would the approach of adding
chip->sw_addr in the smi_direct_{read/write} functions be ok (which
would then require changing the indirect callers to pass 0 instead of
chip->swaddr).

Thanks,
Rasmus