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Date: Fri, 10 May 2019 14:36:31 +0200 From: Andrew Lunn <andrew@...n.ch> To: Michael Grzeschik <mgr@...gutronix.de> Cc: Tristram.Ha@...rochip.com, kernel@...gutronix.de, UNGLinuxDriver@...rochip.com, netdev@...r.kernel.org Subject: Re: [RFC 1/3] mdio-bitbang: add SMI0 mode support > > > +/* Serial Management Interface (SMI) uses the following frame format: > > > + * > > > + * preamble|start|Read/Write| PHY | REG |TA| Data bits | Idle > > > + * |frame| OP code |address |address| | | > > > + * read | 32x1´s | 01 | 00 | 1xRRR | RRRRR |Z0| 00000000DDDDDDDD | Z > > > + * write| 32x1´s | 01 | 00 | 0xRRR | RRRRR |10| xxxxxxxxDDDDDDDD | Z > > > + * > > > + * The register number is encoded with the 5 least significant bits in REG > > > + * and the 3 most significant bits in PHY > > > + */ > > > +#define MII_ADDR_SMI0 (1<<31) > > > + > > > > Michael > > > > This is a Micrel Proprietary protocol. So we should reflect this in > > the name. MII_ADDR_MICREL_SMI? Why the 0? Are there different > > versions? Maybe replace all SMI0 with MICREL_SMI in mdio-bitbang.c > > There are two variants of the SMI interface. Hi Michael O.K, that explains the 0. > > The KSZ8863/73/93 Products use the above Variant described as "SMI0". > > The KSZ8864/95 Products use another layout: > > preamble|start|Read/Write| PHY | REG |TA| Data bits | Idle > |frame| OP code |address |address| | | > read | 32x1´s | 01 | 10 | RR11R | RRRRR |Z0| 00000000DDDDDDDD | Z > write| 32x1´s | 01 | 01 | RR11R | RRRRR |10| xxxxxxxxDDDDDDDD | Z > > So they describe their write/read operation in the OP code rather then > the PHY address. At a first look, i think a standard MDIO bus controller can do this? If so, we don't need a second define, just some code in the switch driver which shuffles bits around. > > We could change the SMI index to SMI_KSZ88X3 for the current SMI0 to > give it a more descriptive name. That seems sensible. In the mv88e6xxx driver, we name things based on the first device to introduce the feature. Andrew
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