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Message-ID: <1557800933-30759-1-git-send-email-biao.huang@mediatek.com>
Date: Tue, 14 May 2019 10:28:49 +0800
From: Biao Huang <biao.huang@...iatek.com>
To: Jose Abreu <joabreu@...opsys.com>, <davem@...emloft.net>
CC: Giuseppe Cavallaro <peppe.cavallaro@...com>,
Alexandre Torgue <alexandre.torgue@...com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Matthias Brugger <matthias.bgg@...il.com>,
<netdev@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <yt.shen@...iatek.com>,
<biao.huang@...iatek.com>, <jianguo.zhang@...iatek.com>
Subject: [v2, PATCH 0/4] fix some bugs in stmmac
changes in v2:
1. update rx_tail_addr as Jose's comment
2. changes clk_csr condition as Alex's proposition
3. remove init lines in dwmac-mediatek, get clk_csr from dts instead.
v1:
This series fix some bugs in stmmac driver
3 patches are for common stmmac or dwmac4:
1. update rx tail pointer to fix rx dma hang issue.
2. change condition for mdc clock to fix csr_clk can't be zero issue.
3. write the modified value back to MTL_OPERATION_MODE.
1 patch is for dwmac-mediatek:
modify csr_clk value to fix mdio read/write fail issue for dwmac-mediatek
Biao Huang (4):
net: stmmac: update rx tail pointer register to fix rx dma hang
issue.
net: stmmac: fix csr_clk can't be zero issue
net: stmmac: write the modified value back to MTL_OPERATION_MODE
net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio
read/write fail
.../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 2 --
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 2 ++
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++++---
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 5 ++++-
4 files changed, 10 insertions(+), 6 deletions(-)
--
1.7.9.5
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