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Date:   Wed, 22 May 2019 20:51:08 +0200
From:   Andrew Lunn <>
To:     Trent Piepho <>
Cc:     "" <>,
        "" <>,
        Florian Fainelli <>,
        Heiner Kallweit <>
Subject: Re: [PATCH net-next v2 3/8] net: phy: dp83867: Add ability to
 disable output clock

On Wed, May 22, 2019 at 06:43:22PM +0000, Trent Piepho wrote:
> Generally, the output clock pin is only used for testing and only serves
> as a source of RF noise after this.  It could be used to daisy-chain
> PHYs, but this is uncommon.  Since the PHY can disable the output, make
> doing so an option.  I do this by adding another enumeration to the
> allowed values of ti,clk-output-sel.
> The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might
> expect: to select the REF_CLK as the output.  Rather it meant "keep
> clock output setting as is", which, depending on PHY strapping, might
> not be outputting REF_CLK.
> Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output.
> Omitting the property will leave the setting as is (which was the
> previous behavior in this case).
> Out of range values were silently converted into
> DP83867_CLK_O_SEL_REF_CLK.  Change this so they generate an error.
> Cc: Andrew Lunn <>
> Cc: Florian Fainelli <>
> Cc: Heiner Kallweit <>
> Signed-off-by: Trent Piepho <>

Reviewed-by: Andrew Lunn <>


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