netdev - Re: [PATCH net-next v2 4/8] net: phy: dp83867: Rework delay rgmii delay handling

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Date:   Wed, 22 May 2019 17:44:15 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     tpiepho@...inj.com
Cc:     netdev@...r.kernel.org, devicetree@...r.kernel.org, andrew@...n.ch,
        f.fainelli@...il.com, hkallweit1@...il.com
Subject: Re: [PATCH net-next v2 4/8] net: phy: dp83867: Rework delay rgmii
 delay handling

From: Trent Piepho <tpiepho@...inj.com>
Date: Wed, 22 May 2019 18:43:23 +0000

> The code was assuming the reset default of the delay control register
> was to have delay disabled.  This is what the datasheet shows as the
> register's initial value.  However, that's not actually true: the
> default is controlled by the PHY's pin strapping.
> 
> If the interface mode is selected as RX or TX delay only, insure the
> other direction's delay is disabled.
> 
> If the interface mode is just "rgmii", with neither TX or RX internal
> delay, one might expect that the driver should disable both delays.  But
> this is not what the driver does.  It leaves the setting at the PHY's
> strapping's default.  And that default, for no pins with strapping
> resistors, is to have delay enabled and 2.00 ns.
> 
> Rather than change this behavior, I've kept it the same and documented
> it.  No delay will most likely not work and will break ethernet on any
> board using "rgmii" mode.  If the board is strapped to have a delay and
> is configured to use "rgmii" mode a warning is generated that "rgmii-id"
> should have been used.
> 
> Also validate the delay values and fail if they are not in range.
> 
> Cc: Andrew Lunn <andrew@...n.ch>
> Cc: Florian Fainelli <f.fainelli@...il.com>
> Cc: Heiner Kallweit <hkallweit1@...il.com>
> Signed-off-by: Trent Piepho <tpiepho@...inj.com>

Applied.