netdev - Re: [PATCH v2 2/4] net: phy: dp83867: increase SGMII autoneg timer duration

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <7da7b818-9006-6208-4d1c-23623a735fb0@gmail.com>
Date:   Mon, 27 May 2019 08:44:19 +0200
From:   Heiner Kallweit <hkallweit1@...il.com>
To:     Max Uvarov <muvarov@...il.com>, netdev@...r.kernel.org
Cc:     andrew@...n.ch, f.fainelli@...il.com, davem@...emloft.net
Subject: Re: [PATCH v2 2/4] net: phy: dp83867: increase SGMII autoneg timer
 duration

On 27.05.2019 08:16, Max Uvarov wrote:
> After reset SGMII Autoneg timer is set to 2us (bits 6 and 5 are 01).
> That us not enough to finalize autonegatiation on some devices.
> Increase this timer duration to maximum supported 16ms.
> 
> Signed-off-by: Max Uvarov <muvarov@...il.com>
> Cc: Heiner Kallweit <hkallweit1@...il.com>
> ---
>  drivers/net/phy/dp83867.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index 75861b8f3b4d..5fafcc091525 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -295,6 +295,16 @@ static int dp83867_config_init(struct phy_device *phydev)
>  				    DP83867_10M_SGMII_CFG, val);
>  		if (ret)
>  			return ret;
> +
> +		/* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
> +		 * are 01). That us not enough to finalize autoneg on some
> +		 * devices. Increase this timer duration to maximum 16ms.
> +		 */
> +		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
> +		val &= ~(BIT(5) | BIT(6));

Using bit numbers directly isn't nice. Better define a mask and constants for
the different combinations of bit 5 and 6 like:
#define FOO_SGMII_ANEG_TIMER_MASK 0x60
#define FOO_SGMII_ANEG_TIMER_2US 0x20
#define FOO_SGMII_ANEG_TIMER_16MS 0x60
And then use the constants in phy_modify_mmd().

> +		ret = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
> +		if (ret)
> +			return ret;
>  	}
>  
>  	/* Enable Interrupt output INT_OE in CFG3 register */
>