netdev - RE: [PATCH net-next v4 5/5] net: stmmac: add EHL SGMII 1Gbps PCI info and PCI ID

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Message-ID: <D6759987A7968C4889FDA6FA91D5CBC814707D4C@PGSMSX103.gar.corp.intel.com>
Date:   Wed, 29 May 2019 18:00:34 +0000
From:   "Voon, Weifeng" <weifeng.voon@...el.com>
To:     Jose Abreu <Jose.Abreu@...opsys.com>,
        "David S. Miller" <davem@...emloft.net>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>
CC:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Giuseppe Cavallaro" <peppe.cavallaro@...com>,
        Andrew Lunn <andrew@...n.ch>,
        "Florian Fainelli" <f.fainelli@...il.com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        biao huang <biao.huang@...iatek.com>,
        "Ong, Boon Leong" <boon.leong.ong@...el.com>,
        "Kweh, Hock Leong" <hock.leong.kweh@...el.com>
Subject: RE: [PATCH net-next v4 5/5] net: stmmac: add EHL SGMII 1Gbps PCI
 info and PCI ID

> 
> > +	plat->axi->axi_lpi_en = 0;
> > +	plat->axi->axi_xit_frm = 0;
> > +	plat->axi->axi_wr_osr_lmt = 0;
> 
> This is not a valid value.

Can you please explained why is not a valid value? And what should
be the recommended value? 
Databook mentioned that "Maximum outstanding requests =
WR_OSR_LMT + 1"

> 
> > +	plat->axi->axi_rd_osr_lmt = 2;
> > +	plat->axi->axi_blen[0] = 4;
> > +	plat->axi->axi_blen[1] = 8;
> > +	plat->axi->axi_blen[2] = 16;
> > +
> > +	/* Set default value for multicast hash bins */
> > +	plat->multicast_filter_bins = HASH_TABLE_SIZE;
> > +
> > +	/* Set default value for unicast filter entries */
> > +	plat->unicast_filter_entries = 1;
> > +
> > +	/* Set the maxmtu to a default of JUMBO_LEN */
> > +	plat->maxmtu = JUMBO_LEN;
> > +
> > +	/* Set 32KB fifo size as the advertised fifo size in
> > +	 * the HW features is not the same as the HW implementation
> > +	 */
> 
> Hmm ? I'm curious, can you explain ?

The RTL comes with a 64KB selection in HW features. But the HW implementation
only uses a 32KB RAM. This will be documented as errata.  

> 
> > +	plat->tx_fifo_size = 32768;
> > +	plat->rx_fifo_size = 32768;
> > +
> > +	return 0;
> > +}
> > +
> > +static int ehl_sgmii1g_data(struct pci_dev *pdev,
> > +			    struct plat_stmmacenet_data *plat) {
> > +	int ret;
> > +
> > +	/* Set common default data first */
> > +	ret = ehl_common_data(pdev, plat);
> > +
> 

Regards
Weifeng