netdev - Re: [PATCH net-next] net: phy: xilinx: add Xilinx PHY driver

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Message-ID: <a03619fb-95f3-e663-f219-a219744c73ef@gmail.com>
Date:   Fri, 31 May 2019 14:11:21 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Robert Hancock <hancock@...systems.ca>, netdev@...r.kernel.org,
        Heiner Kallweit <hkallweit1@...il.com>,
        Andrew Lunn <andrew@...n.ch>
Subject: Re: [PATCH net-next] net: phy: xilinx: add Xilinx PHY driver

On 5/31/19 12:15 PM, Robert Hancock wrote:
> This adds a driver for the PHY device implemented in the Xilinx PCS/PMA
> Core logic. Aside from being a generic gigabit PHY, it includes an
> important register setting to disable the PHY isolation bit, which is
> required for the PHY to operate in 1000BaseX mode.
> 
> This version is a simplified version of the GPL 2+ version from the
> Xilinx kernel tree.
> 
> Signed-off-by: Robert Hancock <hancock@...systems.ca>
> ---
>  drivers/net/phy/Kconfig      |  6 +++++
>  drivers/net/phy/Makefile     |  1 +
>  drivers/net/phy/xilinx_phy.c | 60 ++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 67 insertions(+)
>  create mode 100644 drivers/net/phy/xilinx_phy.c
> 
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index db5645b..101c794 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -462,6 +462,12 @@ config VITESSE_PHY
>  	---help---
>  	  Currently supports the vsc8244
>  
> +config XILINX_PHY
> +	tristate "Drivers for Xilinx PHYs"
> +	help
> +	  This module provides a driver for the PHY implemented in the
> +	  Xilinx PCS/PMA Core.
> +
>  config XILINX_GMII2RGMII
>  	tristate "Xilinx GMII2RGMII converter driver"
>  	---help---
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index bac339e..f71359d 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -92,3 +92,4 @@ obj-$(CONFIG_STE10XP)		+= ste10Xp.o
>  obj-$(CONFIG_TERANETICS_PHY)	+= teranetics.o
>  obj-$(CONFIG_VITESSE_PHY)	+= vitesse.o
>  obj-$(CONFIG_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
> +obj-$(CONFIG_XILINX_PHY)	+= xilinx_phy.o
> diff --git a/drivers/net/phy/xilinx_phy.c b/drivers/net/phy/xilinx_phy.c
> new file mode 100644
> index 0000000..2d468c7
> --- /dev/null
> +++ b/drivers/net/phy/xilinx_phy.c
> @@ -0,0 +1,60 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Xilinx PCS/PMA Core phy driver
> + *
> + * Copyright (C) 2019 SED Systems, a division of Calian Ltd.
> + *
> + * Based upon Xilinx version of this driver:
> + * Copyright (C) 2015 Xilinx, Inc.
> + *
> + * Description:
> + * This driver is developed for PCS/PMA Core.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mii.h>
> +#include <linux/phy.h>
> +
> +/* Mask used for ID comparisons */
> +#define XILINX_PHY_ID_MASK		0xfffffff0
> +
> +/* Known PHY IDs */
> +#define XILINX_PHY_ID			0x01740c00
> +
> +#define XPCSPMA_PHY_CTRL_ISOLATE_DISABLE 0xFBFF
> +
> +static int xilinxphy_config_init(struct phy_device *phydev)
> +{
> +	int temp;
> +
> +	temp = phy_read(phydev, MII_BMCR);
> +	temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE;
> +	phy_write(phydev, MII_BMCR, temp);

The PHY library takes care of clearing the BMCR_ISOLATE bit, is not that
working for you?
-- 
Florian