netdev - [PATCH] net: phy: support C45 phys in SIOCGMIIREG/SIOCSMIIREG ioctls

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20190531074727.3257-1-nikita.yoush@cogentembedded.com>
Date:   Fri, 31 May 2019 10:47:27 +0300
From:   Nikita Yushchenko <nikita.yoush@...entembedded.com>
To:     Andrew Lunn <andrew@...n.ch>,
        Florian Fainelli <f.fainelli@...il.com>
Cc:     Heiner Kallweit <hkallweit1@...il.com>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, Chris Healy <cphealy@...il.com>,
        Nikita Yushchenko <nikita.yoush@...entembedded.com>
Subject: [PATCH] net: phy: support C45 phys in SIOCGMIIREG/SIOCSMIIREG ioctls

This change allows phytool [1] and similar tools to read and write C45 phy
registers from userspace.

This is useful for debugging and for porting vendor phy diagnostics tools.

[1] https://github.com/wkz/phytool

Signed-off-by: Nikita Yushchenko <nikita.yoush@...entembedded.com>
---
 drivers/net/phy/phy.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index e8885429293a..3d991958bde0 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -407,6 +407,7 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
 	struct mii_ioctl_data *mii_data = if_mii(ifr);
 	u16 val = mii_data->val_in;
 	bool change_autoneg = false;
+	int ret;
 
 	switch (cmd) {
 	case SIOCGMIIPHY:
@@ -414,12 +415,28 @@ int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
 		/* fall through */
 
 	case SIOCGMIIREG:
+		if (mdio_phy_id_is_c45(mii_data->phy_id)) {
+			ret = phy_read_mmd(phydev,
+					   mdio_phy_id_devad(mii_data->phy_id),
+					   mii_data->reg_num);
+			if (ret < 0)
+				return ret;
+			mii_data->val_out = ret;
+			return 0;
+		}
 		mii_data->val_out = mdiobus_read(phydev->mdio.bus,
 						 mii_data->phy_id,
 						 mii_data->reg_num);
 		return 0;
 
 	case SIOCSMIIREG:
+		if (mdio_phy_id_is_c45(mii_data->phy_id)) {
+			ret = phy_write_mmd(phydev,
+					    mdio_phy_id_devad(mii_data->phy_id),
+					    mii_data->reg_num,
+					    mii_data->val_in);
+			return ret;
+		}
 		if (mii_data->phy_id == phydev->mdio.addr) {
 			switch (mii_data->reg_num) {
 			case MII_BMCR:
-- 
2.11.0