netdev - Re: [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver

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Message-ID: <2a547fef-880e-fe59-ecff-4e616212a0f7@gmail.com>
Date:   Tue, 4 Jun 2019 19:54:23 +0200
From:   Heiner Kallweit <hkallweit1@...il.com>
To:     Andrew Lunn <andrew@...n.ch>,
        Robert Hancock <hancock@...systems.ca>
Cc:     netdev@...r.kernel.org, Florian Fainelli <f.fainelli@...il.com>
Subject: Re: [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver

On 04.06.2019 18:54, Andrew Lunn wrote:
>> So it seems like what is missing is the ability of genphy_config_init to
>> detect the bits in the extended status register for 1000Base-X and add
>> the corresponding mode flags. It appears bit 15 for 1000Base-X full
>> duplex is standardized in 802.3 Clause 22, so I would expect Linux
>> should be able to detect that and add it as a supported mode for the
>> PHY. genphy_config_init is dealing with the "legacy" 32-bit mode masks
>> that have no bit for 1000BaseX though.. how is that intended to work?
> 
> Hi Robert
> 
> I think you are looking at an old genphy_config_init(). The u32 has
> been replaced. Adding:
> 
> #define ESTATUS_1000_XFULL      0x8000  /* Can do 1000BX Full          */
> #define ESTATUS_1000_XHALF      0x4000  /* Can do 1000BT Half          */
> 
At least so far phylib knows 1000Base-X/Full only. Not sure whether optical
half duplex modes are used in reality.

Detecting 1000Base-X capability is one thing, how about 1000Base-X
advertisement and link partner capability detection?
If I remember the Marvell specs correctly, there was some bit to switch the
complete register set to fibre mode.

Robert, how is this done for the Xilinx PHY?


> and
> 
>                 if (val & ESTATUS_1000_XFULL)
>                         linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
>                                          features);
> 
> should not be a problem.
> 
>        Andrew
>   
>