netdev - [PATCH 1/2] dt-bindings: socfpga-dwmac: add "altr,socfpga-stmmac-a10-s10" binding

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Date:   Wed,  5 Jun 2019 10:05:50 -0500
From:   Dinh Nguyen <dinguyen@...nel.org>
To:     netdev@...r.kernel.org
Cc:     dinguyen@...nel.org, robh+dt@...nel.org, mark.rutland@....com,
        davem@...emloft.net, dalon.westergreen@...el.com
Subject: [PATCH 1/2] dt-bindings: socfpga-dwmac: add "altr,socfpga-stmmac-a10-s10" binding

Add the "altr,socfpga-stmmac-a10-s10" binding for Arria10/Agilex/Stratix10
implementation of the stmmac ethernet controller.

On the Arria10, Agilex, and Stratix10 SoCs, there are a few differences from
the Cyclone5 and Arria5:
     - The emac PHY setup bits are in separate registers.
     - The PTP reference clock select mask is different.
     - The register to enable the emac signal from FPGA is different.

Because of these differences, the dwmac-socfpga glue logic driver will
use this new binding to set the appropriate bits for PHY, PTP reference
clock, and signal from FPGA.

Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
---
 .../devicetree/bindings/net/socfpga-dwmac.txt          | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
index 17d6819669c8..612a8e8abc88 100644
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
@@ -6,11 +6,17 @@ present in Documentation/devicetree/bindings/net/stmmac.txt.
 The device node has additional properties:
 
 Required properties:
- - compatible	: Should contain "altr,socfpga-stmmac" along with
-		  "snps,dwmac" and any applicable more detailed
+ - compatible	: For Cyclone5/Arria5 SoCs it should contain
+		  "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
+		  "altr,socfpga-stmmac-a10-s10".
+		  Along with "snps,dwmac" and any applicable more detailed
 		  designware version numbers documented in stmmac.txt
  - altr,sysmgr-syscon : Should be the phandle to the system manager node that
    encompasses the glue register, the register offset, and the register shift.
+   On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
+   on the Arria10/Stratix10/Agilex platforms, the register shift represents
+   bit for each emac to enable/disable signals from the FPGA fabric to the
+   EMAC modules.
  - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
    for ptp ref clk. This affects all emacs as the clock is common.
 
-- 
2.20.0