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Date: Mon, 24 Jun 2019 20:51:03 +0700 From: Phong Tran <tranmanphong@...il.com> To: tranmanphong@...il.com Cc: acme@...nel.org, alexander.shishkin@...ux.intel.com, alexander.sverdlin@...il.com, allison@...utok.net, andrew@...n.ch, ast@...nel.org, bgolaszewski@...libre.com, bpf@...r.kernel.org, daniel@...earbox.net, daniel@...que.org, dmg@...ingmachine.org, festevam@...il.com, gerg@...inux.org, gregkh@...uxfoundation.org, gregory.clement@...tlin.com, haojian.zhuang@...il.com, hsweeten@...ionengravers.com, illusionist.neo@...il.com, info@...ux.net, jason@...edaemon.net, jolsa@...hat.com, kafai@...com, kernel@...gutronix.de, kgene@...nel.org, krzk@...nel.org, kstewart@...uxfoundation.org, linux-arm-kernel@...ts.infradead.org, linux-imx@....com, linux-kernel@...r.kernel.org, linux-omap@...r.kernel.org, linux-samsung-soc@...r.kernel.org, linux@...linux.org.uk, liviu.dudau@....com, lkundrak@...sk, lorenzo.pieralisi@....com, mark.rutland@....com, mingo@...hat.com, namhyung@...nel.org, netdev@...r.kernel.org, nsekhar@...com, peterz@...radead.org, robert.jarzmik@...e.fr, s.hauer@...gutronix.de, sebastian.hesselbarth@...il.com, shawnguo@...nel.org, songliubraving@...com, sudeep.holla@....com, swinslow@...il.com, tglx@...utronix.de, tony@...mide.com, will@...nel.org, yhs@...com Subject: [PATCH V2 13/15] ARM: mm: cleanup cppcheck shifting errors [arch/arm/mm/alignment.c:875]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour [arch/arm/mm/fault.c:556]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour [arch/arm/mm/fault.c:585]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour [arch/arm/mm/fault.c:219]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour Signed-off-by: Phong Tran <tranmanphong@...il.com> --- arch/arm/mm/fault.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h index c063708fa503..8a706cb7f21d 100644 --- a/arch/arm/mm/fault.h +++ b/arch/arm/mm/fault.h @@ -5,9 +5,9 @@ /* * Fault status register encodings. We steal bit 31 for our own purposes. */ -#define FSR_LNX_PF (1 << 31) -#define FSR_WRITE (1 << 11) -#define FSR_FS4 (1 << 10) +#define FSR_LNX_PF BIT(31) +#define FSR_WRITE BIT(11) +#define FSR_FS4 BIT(10) #define FSR_FS3_0 (15) #define FSR_FS5_0 (0x3f) -- 2.11.0
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