netdev - Re: [PATCH net-next 00/16] bnxt_en: Add TPA (GRO

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Message-ID: <CACKFLimd3aOoYExdUuXBGcTF_r4-hx3S7F8RsBUV72GzAw7SPA@mail.gmail.com>
Date:   Mon, 29 Jul 2019 15:00:01 -0700
From:   Michael Chan <michael.chan@...adcom.com>
To:     David Miller <davem@...emloft.net>
Cc:     Netdev <netdev@...r.kernel.org>
Subject: Re: [PATCH net-next 00/16] bnxt_en: Add TPA (GRO_HW and LRO) on 57500 chips.

On Mon, Jul 29, 2019 at 2:24 PM David Miller <davem@...emloft.net> wrote:
>
> From: Michael Chan <michael.chan@...adcom.com>
> Date: Mon, 29 Jul 2019 06:10:17 -0400
>
> > This patchset adds TPA v2 support on the 57500 chips.  TPA v2 is
> > different from the legacy TPA scheme on older chips and requires major
> > refactoring and restructuring of the existing TPA logic.  The main
> > difference is that the new TPA v2 has on-the-fly aggregation buffer
> > completions before a TPA packet is completed.  The larger aggregation
> > ID space also requires a new ID mapping logic to make it more
> > memory efficient.
>
> Series applied, but please explain something to me.
>
> I thought initially while reviewing this that patch #5 makes the series
> non-bisectable because this only includes the logic that appends new
> entries to the agg array but lacks the changes to reset the agg count
> at TPE end time (which occurs in patch #8).
>
> However I then realized that you haven't turned on the logic yet that
> can result in CMP_TYPE_RX_TPA_AGG_CMP entries in this context.
>
> Am I right?

Yes, correct.  Everything is built up incrementally and the new GRO_HW
and LRO features on the new chip can only be enabled after patch #14.

Thanks.