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Date: Sat, 10 Aug 2019 16:22:23 +0300 From: Andy Shevchenko <andy.shevchenko@...il.com> To: Thomas Bogendoerfer <tbogendoerfer@...e.de> Cc: Ralf Baechle <ralf@...ux-mips.org>, Paul Burton <paul.burton@...s.com>, James Hogan <jhogan@...nel.org>, Dmitry Torokhov <dmitry.torokhov@...il.com>, Lee Jones <lee.jones@...aro.org>, "David S. Miller" <davem@...emloft.net>, Srinivas Kandagatla <srinivas.kandagatla@...aro.org>, Alessandro Zummo <a.zummo@...ertech.it>, Alexandre Belloni <alexandre.belloni@...tlin.com>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby <jslaby@...e.com>, Evgeniy Polyakov <zbr@...emap.net>, linux-mips@...r.kernel.org, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, linux-input <linux-input@...r.kernel.org>, netdev <netdev@...r.kernel.org>, "open list:REAL TIME CLOCK (RTC) SUBSYSTEM" <linux-rtc@...r.kernel.org>, "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org> Subject: Re: [PATCH v4 8/9] MIPS: SGI-IP27: fix readb/writeb addressing On Fri, Aug 9, 2019 at 1:34 PM Thomas Bogendoerfer <tbogendoerfer@...e.de> wrote: > > Our chosen byte swapping, which is what firmware already uses, is to > do readl/writel by normal lw/sw intructions (data invariance). This > also means we need to mangle addresses for u8 and u16 accesses. The > mangling for 16bit has been done aready, but 8bit one was missing. > Correcting this causes different addresses for accesses to the > SuperIO and local bus of the IOC3 chip. This is fixed by changing > byte order in ioc3 and m48rtc_rtc structs. > /* serial port register map */ > struct ioc3_serialregs { > - uint32_t sscr; > - uint32_t stpir; > - uint32_t stcir; > - uint32_t srpir; > - uint32_t srcir; > - uint32_t srtr; > - uint32_t shadow; > + u32 sscr; > + u32 stpir; > + u32 stcir; > + u32 srpir; > + u32 srcir; > + u32 srtr; > + u32 shadow; > }; Isn't it a churn? AFAIU kernel documentation the uint32_t is okay to use, just be consistent inside one module / driver. Am I mistaken? -- With Best Regards, Andy Shevchenko
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