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Message-ID: <CAJpBn1z736w5_uv7apwyy82vzcnc9c5Gua_9ZyUy-pSEwnQewA@mail.gmail.com>
Date: Mon, 26 Aug 2019 08:57:17 -0700
From: Jakub Kicinski <jakub.kicinski@...ronome.com>
To: Song Liu <liu.song.a23@...il.com>
Cc: Alexei Starovoitov <alexei.starovoitov@...il.com>,
Daniel Borkmann <daniel@...earbox.net>,
bpf <bpf@...r.kernel.org>, Networking <netdev@...r.kernel.org>,
OSS Drivers <oss-drivers@...ronome.com>,
Jiong Wang <jiong.wang@...ronome.com>
Subject: Re: [PATCH bpf] nfp: bpf: fix latency bug when updating stack index register
On Sun, Aug 25, 2019 at 10:37 PM Song Liu <liu.song.a23@...il.com> wrote:
> On Fri, Aug 23, 2019 at 7:04 PM Jakub Kicinski wrote:
> > From: Jiong Wang <jiong.wang@...ronome.com>
> >
> > NFP is using Local Memory to model stack. LM_addr could be used as base of
> > a 16 32-bit word region of Local Memory. Then, if the stack offset is
> > beyond the current region, the local index needs to be updated. The update
> > needs at least three cycles to take effect, therefore the sequence normally
> > looks like:
> >
> > local_csr_wr[ActLMAddr3, gprB_5]
> > nop
> > nop
> > nop
> >
> > If the local index switch happens on a narrow loads, then the instruction
> > preparing value to zero high 32-bit of the destination register could be
> > counted as one cycle, the sequence then could be something like:
> >
> > local_csr_wr[ActLMAddr3, gprB_5]
> > nop
> > nop
> > immed[gprB_5, 0]
> >
> > However, we have zero extension optimization that zeroing high 32-bit could
> > be eliminated, therefore above IMMED insn won't be available for which case
> > the first sequence needs to be generated.
> >
> > Fixes: 0b4de1ff19bf ("nfp: bpf: eliminate zero extension code-gen")
> > Signed-off-by: Jiong Wang <jiong.wang@...ronome.com>
> > Reviewed-by: Jakub Kicinski <jakub.kicinski@...ronome.com>
> I haven't looked into the code yet. But ^^^ should be
>
> Signed-off-by: Jakub Kicinski <jakub.kicinski@...ronome.com>
>
> right?
I prefer Review on code I review, ack on code I ack, and sign-off on
code I co-author.
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