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Message-ID: <mhng-c8a768f7-1a90-4228-b654-be9e879c92ec@palmer-si-x1c4>
Date: Tue, 03 Sep 2019 15:27:12 -0700 (PDT)
From: Palmer Dabbelt <palmer@...ive.com>
To: luto@...capital.net
CC: keescook@...omium.org, david.abdurachmanov@...il.com,
Paul Walmsley <paul.walmsley@...ive.com>,
aou@...s.berkeley.edu, oleg@...hat.com, wad@...omium.org,
shuah@...nel.org, ast@...nel.org, daniel@...earbox.net,
kafai@...com, songliubraving@...com, yhs@...com,
David Abdurachmanov <david.abdurachmanov@...ive.com>,
tglx@...utronix.de, allison@...utok.net, alexios.zavras@...el.com,
Anup Patel <Anup.Patel@....com>, vincentc@...estech.com,
alankao@...estech.com, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-kselftest@...r.kernel.org,
netdev@...r.kernel.org, bpf@...r.kernel.org, me@...losedp.com
Subject: Re: [PATCH v2] riscv: add support for SECCOMP and SECCOMP_FILTER
On Wed, 28 Aug 2019 10:52:05 PDT (-0700), luto@...capital.net wrote:
>
>
>> On Aug 25, 2019, at 2:59 PM, Kees Cook <keescook@...omium.org> wrote:
>>
>>> On Thu, Aug 22, 2019 at 01:55:22PM -0700, David Abdurachmanov wrote:
>>> This patch was extensively tested on Fedora/RISCV (applied by default on
>>> top of 5.2-rc7 kernel for <2 months). The patch was also tested with 5.3-rc
>>> on QEMU and SiFive Unleashed board.
>>
>> Oops, I see the mention of QEMU here. Where's the best place to find
>> instructions on creating a qemu riscv image/environment?
>
> I don’t suppose one of you riscv folks would like to contribute riscv support to virtme? virtme-run —arch=riscv would be quite nice, and the total patch should be just a couple lines. Unfortunately, it helps a lot to understand the subtleties of booting the architecture to write those couple lines :)
What mailing list should I sent this to? You need to use the "virtme" branch
of kernel.org/palmer/linux.git until I send the defconfig patches.
commit a8bd7b318691891991caea298f9a5ed0f815c322
gpg: Signature made Tue 03 Sep 2019 03:22:45 PM PDT
gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
gpg: issuer "palmer@...belt.com"
gpg: Good signature from "Palmer Dabbelt <palmer@...belt.com>" [ultimate]
gpg: aka "Palmer Dabbelt <palmer@...ive.com>" [ultimate]
Author: Palmer Dabbelt <palmer@...ive.com>
Date: Tue Sep 3 14:39:39 2019 -0700
Add RISC-V support
This expects a kernel with the plan 9 stuff supported (not yet in
defconfig) and a new QEMU (as described in the README). I'm also not
100% sure it's working, as I'm getting
/bin/sh: exec: line 1: /run/virtme/guesttools/virtme-init: not found
Signed-off-by: Palmer Dabbelt <palmer@...ive.com>
diff --git a/README.md b/README.md
index 51b6583..d53a456 100644
--- a/README.md
+++ b/README.md
@@ -112,6 +112,14 @@ PPC64
PPC64 appears to be reasonably functional.
+RISC-V
+------
+
+riscv64 works out of the box, but you'll neet at least QEMU-4.1.0 to be
+able to run `vmlinux`-style kernels. riscv32 is not supported because
+there are no existing userspace images for it. Support is provided via
+QEMU's `virt` machine with OpenSBI for firmware.
+
Others
------
diff --git a/virtme/architectures.py b/virtme/architectures.py
index 9871ea4..ee84494 100644
--- a/virtme/architectures.py
+++ b/virtme/architectures.py
@@ -207,6 +207,30 @@ class Arch_ppc64(Arch):
# Apparently SLOF (QEMU's bundled firmware?) can't boot a zImage.
return 'vmlinux'
+class Arch_riscv64(Arch):
+ def __init__(self, name):
+ Arch.__init__(self, name)
+
+ self.defconfig_target = 'riscv64_defconfig'
+ self.qemuname = 'riscv64'
+ self.linuxname = 'riscv'
+ self.gccname = 'riscv64'
+
+ def qemuargs(self, is_native):
+ ret = Arch.qemuargs(is_native)
+
+ ret.extend(['-machine', 'virt'])
+ ret.extend(['-bios', 'default'])
+
+ return ret
+
+ @staticmethod
+ def serial_console_args():
+ return ['console=ttyS0']
+
+ def kimg_path(self):
+ return 'arch/riscv/boot/Image'
+
class Arch_sparc64(Arch):
def __init__(self, name):
Arch.__init__(self, name)
@@ -264,6 +288,7 @@ ARCHES = {
'arm': Arch_arm,
'aarch64': Arch_aarch64,
'ppc64': Arch_ppc64,
+ 'riscv64': Arch_riscv64,
'sparc64': Arch_sparc64,
's390x': Arch_s390x,
}
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