netdev - RE: [PATCH v3 net-next] net: stmmac: Add support for MDIO interrupts

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Message-ID: <BN8PR12MB3266F79F6ECCCFCA6D844F4FD3BA0@BN8PR12MB3266.namprd12.prod.outlook.com>
Date:   Fri, 6 Sep 2019 14:33:57 +0000
From:   Jose Abreu <Jose.Abreu@...opsys.com>
To:     Andrew Lunn <andrew@...n.ch>, Jose Abreu <Jose.Abreu@...opsys.com>
CC:     Voon Weifeng <weifeng.voon@...el.com>,
        "David S. Miller" <davem@...emloft.net>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Giuseppe Cavallaro" <peppe.cavallaro@...com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        Ong Boon Leong <boon.leong.ong@...el.com>
Subject: RE: [PATCH v3 net-next] net: stmmac: Add support for MDIO interrupts

From: Andrew Lunn <andrew@...n.ch>
Date: Sep/06/2019, 15:24:46 (UTC+00:00)

> On Fri, Sep 06, 2019 at 01:31:14PM +0000, Jose Abreu wrote:
> > From: Voon Weifeng <weifeng.voon@...el.com>
> > Date: Sep/05/2019, 13:05:30 (UTC+00:00)
> > 
> > > DW EQoS v5.xx controllers added capability for interrupt generation
> > > when MDIO interface is done (GMII Busy bit is cleared).
> > > This patch adds support for this interrupt on supported HW to avoid
> > > polling on GMII Busy bit.
> > 
> > Better leave the enabling of this optional because the support for it is 
> > also optional depending on the IP HW configuration.
> 
> Hi Jose
> 
> If there a register which indicates if this feature is part of the IP?

Yes. That would be SMASEL which is Bit 5 of register MAC_HW_Feature0.

---
Thanks,
Jose Miguel Abreu