netdev - Re: [PATCH v4 2/2] net: phy: dp83867: Add SGMII mode type switching

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Date:   Mon, 9 Sep 2019 17:40:11 +0000
From:   Trent Piepho <tpiepho@...inj.com>
To:     "vitaly.gaiduk@...udbear.ru" <vitaly.gaiduk@...udbear.ru>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "f.fainelli@...il.com" <f.fainelli@...il.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>
CC:     "mark.rutland@....com" <mark.rutland@....com>,
        "hkallweit1@...il.com" <hkallweit1@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "andrew@...n.ch" <andrew@...n.ch>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 2/2] net: phy: dp83867: Add SGMII mode type switching

On Mon, 2019-09-09 at 20:19 +0300, Vitaly Gaiduk wrote:
> This patch adds ability to switch beetween two PHY SGMII modes.
> Some hardware, for example, FPGA IP designs may use 6-wire mode
> which enables differential SGMII clock to MAC.
> 
> +
> +		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
> +		/* SGMII type is set to 4-wire mode by default.
> +		 * If we place appropriate property in dts (see above)
> +		 * switch on 6-wire mode.
> +		 */
> +		if (dp83867->sgmii_ref_clk_en)
> +			val |= DP83867_SGMII_TYPE;
> +		else
> +			val &= ~DP83867_SGMII_TYPE;
> +		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);

Should use phy_modify_mmd().