netdev - dp83867: Why does ti,fifo-depth set only TX, and why is it mandatory?

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Message-ID: <20191114162431.GA21979@localhost>
Date:   Thu, 14 Nov 2019 18:24:32 +0200
From:   Adrian Bunk <bunk@...nel.org>
To:     Dan Murphy <dmurphy@...com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>, netdev@...r.kernel.org
Subject: dp83867: Why does ti,fifo-depth set only TX, and why is it mandatory?

Hi,

looking at the ti,fifo-depth property to set the TX FIFO Depth in the 
dp83867 driver I was wondering:

1. Why does it set only TX?
Is there a reason why TX needs setting but RX does not?
(RX FIFO Depth is SGMII-only, but that's what I am using)

2. Why is it a mandatory property?
Perhaps I am missing something obvious, but why can't the driver either
leave the value untouched or set the maximum when nothing is configured?

Thanks in advance
Adrian