netdev - Re: [PATCH v3 net-next 2/3] net: page_pool: add the possibility to sync DMA memory for device

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Date:   Sat, 16 Nov 2019 12:20:17 +0100
From:   Jesper Dangaard Brouer <brouer@...hat.com>
To:     Lorenzo Bianconi <lorenzo@...nel.org>
Cc:     netdev@...r.kernel.org, davem@...emloft.net,
        ilias.apalodimas@...aro.org, lorenzo.bianconi@...hat.com,
        mcroce@...hat.com, brouer@...hat.com
Subject: Re: [PATCH v3 net-next 2/3] net: page_pool: add the possibility to
 sync DMA memory for device

On Fri, 15 Nov 2019 21:01:38 +0200
Lorenzo Bianconi <lorenzo@...nel.org> wrote:

>  static bool __page_pool_recycle_into_ring(struct page_pool *pool,
> -				   struct page *page)
> +					  struct page *page,
> +					  unsigned int dma_sync_size)
>  {
>  	int ret;
>  	/* BH protection not needed if current is serving softirq */
> @@ -264,6 +285,9 @@ static bool __page_pool_recycle_into_ring(struct page_pool *pool,
>  	else
>  		ret = ptr_ring_produce_bh(&pool->ring, page);
>  
> +	if (ret == 0 && (pool->p.flags & PP_FLAG_DMA_SYNC_DEV))
> +		page_pool_dma_sync_for_device(pool, page, dma_sync_size);
> +
>  	return (ret == 0) ? true : false;
>  }


I do wonder if we should DMA-sync-for-device BEFORE putting page into
ptr_ring, as this is a channel between several concurrent CPUs.



> @@ -273,18 +297,22 @@ static bool __page_pool_recycle_into_ring(struct page_pool *pool,
>   * Caller must provide appropriate safe context.
>   */
>  static bool __page_pool_recycle_direct(struct page *page,
> -				       struct page_pool *pool)
> +				       struct page_pool *pool,
> +				       unsigned int dma_sync_size)
>  {
>  	if (unlikely(pool->alloc.count == PP_ALLOC_CACHE_SIZE))
>  		return false;
>  
>  	/* Caller MUST have verified/know (page_ref_count(page) == 1) */
>  	pool->alloc.cache[pool->alloc.count++] = page;
> +
> +	if (pool->p.flags & PP_FLAG_DMA_SYNC_DEV)
> +		page_pool_dma_sync_for_device(pool, page, dma_sync_size);
>  	return true;
>  }

We know __page_pool_recycle_direct() is concurrency safe, and only a
single (NAPI processing) CPU can enter. (So, the DMA-sync order is not
wrong here, but it could be swapped)

-- 
Best regards,
  Jesper Dangaard Brouer
  MSc.CS, Principal Kernel Engineer at Red Hat
  LinkedIn: http://www.linkedin.com/in/brouer