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Date:   Sun, 15 Dec 2019 13:10:19 +0200
From:   Baruch Siach <>
To:     Marek Behun <>
Cc:     Andrew Lunn <>,
        Vivien Didelot <>,,
        Denis Odintsov <>,
        Hubert Feurstein <>
Subject: Re: [BUG] mv88e6xxx: tx regression in v5.3

Hi Marek,

On Sun, Dec 15 2019, Baruch Siach wrote:
> The call to mv88e6341_port_set_cmode() introduced in commit 7a3007d22e8
> ("net: dsa: mv88e6xxx: fully support SERDES on Topaz family") still
> breaks port 5 (cpu) configuration. When called, its mode parameter is
> set to PHY_INTERFACE_MODE_2500BASEX (19).
> Any idea?

I dug a little further here. It turns out that
mv88e6xxx_port_set_cmode() does not do any register write, because it
exits early here with cmode == 0xb:

        /* cmode doesn't change, nothing to do for us */
        if (cmode == chip->ports[port].cmode)
                return 0;

mv88e6341_port_set_cmode_writable() breaks the port configuration with
its call to mv88e6xxx_port_hidden_write(). Before this call
mv88e6352_port_get_cmode() sets cmode to 0xb. After this call cmode is
6. This breaks the assumption that the equality test above relies on.

This fixes cpu port configuration for me:

diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 7fe256c5739d..a6c320978bcf 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -427,10 +427,6 @@ static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 		cmode = 0;
-	/* cmode doesn't change, nothing to do for us */
-	if (cmode == chip->ports[port].cmode)
-		return 0;
 	lane = mv88e6xxx_serdes_get_lane(chip, port);
 	if (lane) {
 		if (chip->ports[port].serdes_irq) {

Does that make sense?


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