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Date:   Sun, 15 Dec 2019 15:57:14 +0100
From:   Oleksij Rempel <o.rempel@...gutronix.de>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Mark Rutland <mark.rutland@....com>, devicetree@...r.kernel.org,
        Jay Cliburn <jcliburn@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Chris Snook <chris.snook@...il.com>,
        linux-kernel@...r.kernel.org, Ralf Baechle <ralf@...ux-mips.org>,
        "David S. Miller" <davem@...emloft.net>,
        Paul Burton <paul.burton@...s.com>,
        Rob Herring <robh+dt@...nel.org>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        James Hogan <jhogan@...nel.org>,
        Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
        linux-mips@...r.kernel.org,
        Vivien Didelot <vivien.didelot@...il.com>
Subject: Re: [PATCH v4 2/5] dt-bindings: net: dsa: qca,ar9331 switch
 documentation

Hi Andrew,

On Tue, Oct 29, 2019 at 08:34:19AM +0100, Oleksij Rempel wrote:
> On Wed, Oct 23, 2019 at 02:35:43AM +0200, Andrew Lunn wrote:
> > On Tue, Oct 22, 2019 at 07:57:40AM +0200, Oleksij Rempel wrote:
> > > Atheros AR9331 has built-in 5 port switch. The switch can be configured
> > > to use all 5 or 4 ports. One of built-in PHYs can be used by first built-in
> > > ethernet controller or to be used directly by the switch over second ethernet
> > > controller.
> > > 
> > > Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
> > 
> > Hi Oleksij
> > 
> > What we never really discussed is how this MUXing of the PHY works.
> > 
> > What i'm worried about is that when we do understand how it works, we
> > cannot properly support it using this binding.
> 
> good point. i would prefer to make it properly.
> 
> > Please could you try to find information about this.
> 
> Documentation says:
> The PHY interfaces (PHY0, PHY1, PHY2, PHY3 and PHY4) can connect to the switch
> in bridge mode. In this case GE0 must be under reset. All five LAN ports are
> switched together and connect to the CPU through the GMII interface (MAC0),
> which is controlled by the ETH_CFG register bit SW_ONLY_MODE. If GE0 connects
> separately to PHY, then MAC5 should be under reset.
> 
> There is no SW_ONLY_MODE bit in the documentation.
> I found:
> CFG_SW_PHY_SWAP - Used to switch the wires connection of PHY port 0 with that of
> port 4 in the Ethernet switch. MAC1 and PHY4 are paired while MAC5 and PHY0 are
> paired.
> 
> CFG_SW_PHY_ADDR_SWAP - Exchanges the address of PHY port 0 with that of
> PHY port 4 in the Ethernet switch.
> 
> It feels like this are the right bits. I'll try to test it after ELC-E
> conference (If you are here, please ping me).
> If this are the right bits, should it be registered as separate driver? This
> register is on MMIO and not part of the switches MDIO.

I spend some tine on investigating and testing it. So, the result is
pretty simple. It looks like *MII lines of ethernet controller GMAC0 and
MAC of switch port5 are just connected together and wired to the PHY4.
Something like this:

GMAC1-->switch--mac5-+--->phy4
                     ^
GMAC0---------------/


So, both of MACs can be enabled at same time and introduce resource
conflict. If one is enabled, other one should be set in to reset mode.

The questions are:
- how this can be reflected in devicetree?
- how this can be properly implemented in kernel?

Regards,
Oleksij
-- 
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