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Message-ID: <1cb77c2dcfeb495c9e7c417edd7f43cc@AcuMS.aculab.com>
Date: Mon, 16 Dec 2019 16:45:35 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Björn Töpel' <bjorn.topel@...il.com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"ast@...nel.org" <ast@...nel.org>,
"daniel@...earbox.net" <daniel@...earbox.net>
CC: Björn Töpel <bjorn.topel@...el.com>,
"bpf@...r.kernel.org" <bpf@...r.kernel.org>,
"magnus.karlsson@...il.com" <magnus.karlsson@...il.com>,
"magnus.karlsson@...el.com" <magnus.karlsson@...el.com>,
"jonathan.lemon@...il.com" <jonathan.lemon@...il.com>,
"ecree@...arflare.com" <ecree@...arflare.com>,
"thoiland@...hat.com" <thoiland@...hat.com>,
"brouer@...hat.com" <brouer@...hat.com>,
"andrii.nakryiko@...il.com" <andrii.nakryiko@...il.com>
Subject: RE: [PATCH bpf-next v5 6/6] bpf, x86: align dispatcher branch targets
to 16B
From: Björn Töpel
> Sent: 13 December 2019 17:51
> From: Björn Töpel <bjorn.topel@...el.com>
>
> From Intel 64 and IA-32 Architectures Optimization Reference Manual,
> 3.4.1.4 Code Alignment, Assembly/Compiler Coding Rule 11: All branch
> targets should be 16-byte aligned.
>
> This commits aligns branch targets according to the Intel manual.
I'd Ignore that advice....
It makes very little difference, and none at all on more recent cpu.
Read https://www.agner.org/optimize/microarchitecture.pdf
The extra cache footprint probably makes a bigger difference.
David
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