Message-Id: <20191217221831.10923-1-olteanv@gmail.com>
Date:   Wed, 18 Dec 2019 00:18:23 +0200
From:   Vladimir Oltean <olteanv@...il.com>
To:     davem@...emloft.net, jakub.kicinski@...ronome.com,
        linux@...linux.org.uk, andrew@...n.ch, f.fainelli@...il.com,
        vivien.didelot@...il.com
Cc:     alexandru.marginean@....com, claudiu.manoil@....com,
        xiaoliang.yang_1@....com, yangbo.lu@....com,
        netdev@...r.kernel.org, alexandre.belloni@...tlin.com,
        horatiu.vultur@...rochip.com,
        Vladimir Oltean <vladimir.oltean@....com>
Subject: [RFC PATCH v2 0/8] Convert Felix DSA switch to PHYLINK

From: Vladimir Oltean <vladimir.oltean@....com>

Unlike most other conversions, and unlike this series' own v1 [0] from which it
is radically different, this conversion is not by far a trivial one, and should
be seen as "Layerscape PCS meets PHYLINK". Depending on the feedback received,
the PCS driver from felix_vsc9959 can in fact be generalized to cover most of
the Layerscape devices, or we can scrap the idea.  Actually, the PCS doesn't
need a lot of hand-holding and most of our other devices 'just work' (this one
included) without any sort of operating system awareness, just an
initialization procedure done typically in the bootloader.

The PCS is not specific to the Vitesse / Microsemi / Microchip switching core
at all. Variations of this SerDes/PCS design can also be found on DPAA1 and
DPAA2 hardware.

The main idea of the abstraction provided is that the PCS looks so much like a
PHY device, that we model it as an actual PHY device and run the generic PHY
functions on it, where appropriate.

The 4xSGMII, QSGMII and QSXGMII modes are fairly straightforward.

The SerDes protocol which the driver calls 2500Base-X mode (a misnomer) is more
interesting. There is a description of how it works and what can be done with
it in patch 8/8 (in a comment above vsc9959_pcs_init_2500basex).
In short, it is a fixed speed protocol with no auto-negotiation whatsoever.
>From my research of the SGMII-2500 patent [1], it has nothing to do with
SGMII-2500. That one:
* does not define any change to the AN base page compared to plain 10/100/1000
  SGMII. This implies that the 2500 speed is not negotiable, but the other
  speeds are. In our case, when the SerDes is configured for this protocol it's
  configured for good, there's no going back to SGMII.
* runs at a higher base frequency than regular SGMII. So SGMII-2500 operating
  at 1000 Mbps wouldn't interoperate with plain SGMII at 1000 Mbps. Strange,
  but ok..
* Emulates lower link speeds than 2500 by duplicating the codewords twice, then
  thrice, then twice again etc (2.5/25/250 times on average). The Layerscape
  PCS doesn't do that (it is fixed at 2500 Mbaud).

But on the other hand it isn't Base-X either, since it doesn't do 802.3z /
clause 37 auto negotiation (flow control, local/remote fault etc).

So it is a protocol in its own right (a rather fixed one). If reviewers think
it should have its own phy-mode, different than 2500base-x, I'm in favor of
that. It's just that I couldn't find a suitable name for it. quarter-xaui?
3125mhz-8b10b?

When inter-operating with the Aquantia AQR112 and AQR412 PHYs in this mode (for
which the PHY uses a proprietary name "OCSGMII"), we do still need to support
the lower link speeds negotiated by the PHY on copper side. So what we
typically do is we enable rate adaptation in the PHY firmware, with pause
frames and a fixed link speed on the system side. Raising this as a discussion
item to understand how we can model this quirky operating mode in Linux without
imposing limitations on others (we have some downstream patches on the Aquantia
PHY driver as well).

Another item to discuss is whether we should be able to disable AN in the PCS
independently of whether we have a PHY as a peer or not. With an SGMII PHY-less
connection, there may be no auto-negotiation master so the link partners will
bounce for a while and then they'll settle on 10 Mbps as link speed. For those
connections (such as an SGMII link to a downstream switch) we need to disable
AN in the PCS and force the speed to 1000.
So:
* If we have a PHY we want to do auto-neg
* If we don't have a PHY, maybe we want AN, maybe we don't
* In the 2500Base-X mode, we can't do AN because the hardware doesn't support it

I have found the 'managed = "in-band-status"' DTS binding to somewhat address
this concern, but I am a bit reluctant to disable SGMII AN if it isn't set.
We have boards with device trees that need to be migrated from PHYLIB and I
am concerned that changing the behavior w.r.t. in-band AN (when the
"in-band-status" property is not present) is not going to be pleasant.
I do understand that the "in-band-status" property is primarily intended to be
used with PHY-less setups, and it looks like the fact it does work with PHYs as
well is more of an oversight (as patch 2/8 shows). So I'm not sure who else
really uses it with a phy-handle.

There are some more open questions in patch 8/8.

I dropped the Ocelot PHYLINK conversion because:
* I don't have VSC7514 hardware anyway
* The hardware is so different in this regard that there's almost nothing to
  share anyway.

[0]: https://www.spinics.net/lists/netdev/msg613869.html
[1]: https://patents.google.com/patent/US7356047B1/en

Claudiu Manoil (1):
  enetc: Make MDIO accessors more generic and export to
    include/linux/fsl

Vladimir Oltean (7):
  mii: Add helpers for parsing SGMII auto-negotiation
  net: phylink: make QSGMII a valid PHY mode for in-band AN
  net: phylink: call mac_an_restart for SGMII/QSGMII inband interfaces
    too
  enetc: Set MDIO_CFG_HOLD to the recommended value of 2
  net: mscc: ocelot: make phy_mode a member of the common struct
    ocelot_port
  net: mscc: ocelot: export ANA, DEV and QSYS registers to
    include/soc/mscc
  net: dsa: felix: Add PCS operations for PHYLINK

 drivers/net/dsa/ocelot/Kconfig                     |   1 +
 drivers/net/dsa/ocelot/felix.c                     | 260 ++++++++-
 drivers/net/dsa/ocelot/felix.h                     |  16 +-
 drivers/net/dsa/ocelot/felix_vsc9959.c             | 475 +++++++++++++++-
 drivers/net/ethernet/freescale/enetc/enetc_hw.h    |   1 +
 drivers/net/ethernet/freescale/enetc/enetc_mdio.c  |  88 ++-
 drivers/net/ethernet/freescale/enetc/enetc_mdio.h  |  12 -
 .../net/ethernet/freescale/enetc/enetc_pci_mdio.c  |  43 +-
 drivers/net/ethernet/mscc/ocelot.c                 |   7 +-
 drivers/net/ethernet/mscc/ocelot.h                 |   7 +-
 drivers/net/ethernet/mscc/ocelot_ana.h             | 625 ---------------------
 drivers/net/ethernet/mscc/ocelot_board.c           |   4 +-
 drivers/net/ethernet/mscc/ocelot_dev.h             | 275 ---------
 drivers/net/ethernet/mscc/ocelot_qsys.h            | 270 ---------
 drivers/net/phy/phylink.c                          |   5 +-
 include/linux/fsl/enetc_mdio.h                     |  34 ++
 include/linux/mii.h                                |  50 ++
 include/soc/mscc/ocelot.h                          |   2 +
 include/soc/mscc/ocelot_ana.h                      | 625 +++++++++++++++++++++
 include/soc/mscc/ocelot_dev.h                      | 275 +++++++++
 include/soc/mscc/ocelot_qsys.h                     | 270 +++++++++
 include/uapi/linux/mii.h                           |  10 +
 22 files changed, 2100 insertions(+), 1255 deletions(-)
 delete mode 100644 drivers/net/ethernet/freescale/enetc/enetc_mdio.h
 delete mode 100644 drivers/net/ethernet/mscc/ocelot_ana.h
 delete mode 100644 drivers/net/ethernet/mscc/ocelot_dev.h
 delete mode 100644 drivers/net/ethernet/mscc/ocelot_qsys.h
 create mode 100644 include/linux/fsl/enetc_mdio.h
 create mode 100644 include/soc/mscc/ocelot_ana.h
 create mode 100644 include/soc/mscc/ocelot_dev.h
 create mode 100644 include/soc/mscc/ocelot_qsys.h

-- 
2.7.4

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