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Date: Thu, 26 Dec 2019 11:21:14 +0000
From: "Y.b. Lu" <yangbo.lu@....com>
To: Vladimir Oltean <olteanv@...il.com>
CC: netdev <netdev@...r.kernel.org>,
"David S . Miller" <davem@...emloft.net>,
Claudiu Manoil <claudiu.manoil@....com>,
Vladimir Oltean <vladimir.oltean@....com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
Richard Cochran <richardcochran@...il.com>
Subject: RE: [PATCH] net: mscc: ocelot: support PPS signal generation
> -----Original Message-----
> From: Vladimir Oltean <olteanv@...il.com>
> Sent: Thursday, December 26, 2019 6:50 PM
> To: Y.b. Lu <yangbo.lu@....com>
> Cc: netdev <netdev@...r.kernel.org>; David S . Miller
> <davem@...emloft.net>; Claudiu Manoil <claudiu.manoil@....com>;
> Vladimir Oltean <vladimir.oltean@....com>; Alexandre Belloni
> <alexandre.belloni@...tlin.com>; Microchip Linux Driver Support
> <UNGLinuxDriver@...rochip.com>; Richard Cochran
> <richardcochran@...il.com>
> Subject: Re: [PATCH] net: mscc: ocelot: support PPS signal generation
>
> On Thu, 26 Dec 2019 at 12:49, Vladimir Oltean <olteanv@...il.com> wrote:
> >
> > Hi Yangbo,
> >
> > On Thu, 26 Dec 2019 at 12:00, Yangbo Lu <yangbo.lu@....com> wrote:
> > >
> > > This patch is to support PPS signal generation for Ocelot family
> > > switches, including VSC9959 switch.
> > >
> > > Signed-off-by: Yangbo Lu <yangbo.lu@....com>
> > > ---
> >
> > Shouldn't this be integrated with the .enable callback of the PTP core?
> >
> > > drivers/net/dsa/ocelot/felix_vsc9959.c | 2 ++
> > > drivers/net/ethernet/mscc/ocelot.c | 25
> +++++++++++++++++++++++++
> > > drivers/net/ethernet/mscc/ocelot_ptp.h | 2 ++
> > > drivers/net/ethernet/mscc/ocelot_regs.c | 2 ++
> > > include/soc/mscc/ocelot.h | 2 ++
> > > 5 files changed, 33 insertions(+)
> > >
> > > diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c
> b/drivers/net/dsa/ocelot/felix_vsc9959.c
> > > index b9758b0..ee0ce7c 100644
> > > --- a/drivers/net/dsa/ocelot/felix_vsc9959.c
> > > +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c
> > > @@ -287,6 +287,8 @@ static const u32 vsc9959_ptp_regmap[] = {
> > > REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
> > > REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
> > > REG(PTP_PIN_TOD_NSEC, 0x00000c),
> > > + REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
> > > + REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
> > > REG(PTP_CFG_MISC, 0x0000a0),
> > > REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
> > > REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
> > > diff --git a/drivers/net/ethernet/mscc/ocelot.c
> b/drivers/net/ethernet/mscc/ocelot.c
> > > index 985b46d..c0f8a9e 100644
> > > --- a/drivers/net/ethernet/mscc/ocelot.c
> > > +++ b/drivers/net/ethernet/mscc/ocelot.c
> > > @@ -2147,6 +2147,29 @@ static struct ptp_clock_info
> ocelot_ptp_clock_info = {
> > > .adjfine = ocelot_ptp_adjfine,
> > > };
> > >
> > > +static void ocelot_ptp_init_pps(struct ocelot *ocelot)
> > > +{
> > > + u32 val;
> > > +
> > > + /* PPS signal generation uses CLOCK action. Together with SYNC
> option,
> > > + * a single pulse will be generated after <WAFEFORM_LOW>
> nanoseconds
> > > + * after the time of day has increased the seconds. The pulse will
> > > + * get a width of <WAFEFORM_HIGH> nanoseconds.
> >
> > Also, I think what you have implemented here is periodic output
> > (PTP_CLK_REQ_PEROUT) not PPS [input] (PTP_CLK_REQ_PPS). I have found
> > the PTP documentation to be rather confusing on what PTP_CLK_REQ_PPS
> > means, so I'm adding Richard in the hope that he may clarify (also
> > what's different between PTP_CLK_REQ_PPS and PTP_CLK_REQ_PPS).
>
> EXTTS, sorry, obviously nothing is different between X and itself.
>
EXTTS is for capturing timestamps for external trigger pin which is input signal.
> >
> > > + *
> > > + * In default,
> > > + * WAFEFORM_LOW = 0
> > > + * WAFEFORM_HIGH = 1us
> > > + */
> > > + ocelot_write_rix(ocelot, 0, PTP_PIN_WF_LOW_PERIOD,
> ALT_PPS_PIN);
> > > + ocelot_write_rix(ocelot, 1000, PTP_PIN_WF_HIGH_PERIOD,
> ALT_PPS_PIN);
> > > +
> > > + val = ocelot_read_rix(ocelot, PTP_PIN_CFG, ALT_PPS_PIN);
> > > + val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK |
> PTP_PIN_CFG_DOM);
> > > + val |= (PTP_PIN_CFG_SYNC |
> PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_CLOCK));
> > > +
> >
> > I suppose the reason why you didn't use ocelot_rmw_rix here is that it
> > doesn't fit in 80 characters?
> > Do you even need to read-modify-write? The only other field is the
> > polarity bit which is by default 0 (active high) and non-configurable
> > via the current API (struct ptp_pin_desc) as far as I can see.
> >
> > > + ocelot_write_rix(ocelot, val, PTP_PIN_CFG, ALT_PPS_PIN);
> > > +}
> > > +
> > > static int ocelot_init_timestamp(struct ocelot *ocelot)
> > > {
> > > struct ptp_clock *ptp_clock;
> > > @@ -2478,6 +2501,8 @@ int ocelot_init(struct ocelot *ocelot)
> > > "Timestamp initialization failed\n");
> > > return ret;
> > > }
> > > +
> > > + ocelot_ptp_init_pps(ocelot);
> > > }
> > >
> > > return 0;
> > > diff --git a/drivers/net/ethernet/mscc/ocelot_ptp.h
> b/drivers/net/ethernet/mscc/ocelot_ptp.h
> > > index 9ede14a..21bc744 100644
> > > --- a/drivers/net/ethernet/mscc/ocelot_ptp.h
> > > +++ b/drivers/net/ethernet/mscc/ocelot_ptp.h
> > > @@ -13,6 +13,8 @@
> > > #define PTP_PIN_TOD_SEC_MSB_RSZ
> PTP_PIN_CFG_RSZ
> > > #define PTP_PIN_TOD_SEC_LSB_RSZ PTP_PIN_CFG_RSZ
> > > #define PTP_PIN_TOD_NSEC_RSZ PTP_PIN_CFG_RSZ
> > > +#define PTP_PIN_WF_HIGH_PERIOD_RSZ PTP_PIN_CFG_RSZ
> > > +#define PTP_PIN_WF_LOW_PERIOD_RSZ PTP_PIN_CFG_RSZ
> > >
> > > #define PTP_PIN_CFG_DOM BIT(0)
> > > #define PTP_PIN_CFG_SYNC BIT(2)
> > > diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c
> b/drivers/net/ethernet/mscc/ocelot_regs.c
> > > index b88b589..ed4dd01 100644
> > > --- a/drivers/net/ethernet/mscc/ocelot_regs.c
> > > +++ b/drivers/net/ethernet/mscc/ocelot_regs.c
> > > @@ -239,6 +239,8 @@ static const u32 ocelot_ptp_regmap[] = {
> > > REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
> > > REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
> > > REG(PTP_PIN_TOD_NSEC, 0x00000c),
> > > + REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
> > > + REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
> > > REG(PTP_CFG_MISC, 0x0000a0),
> > > REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
> > > REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
> > > diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h
> > > index 64cbbbe..c2ab20d 100644
> > > --- a/include/soc/mscc/ocelot.h
> > > +++ b/include/soc/mscc/ocelot.h
> > > @@ -325,6 +325,8 @@ enum ocelot_reg {
> > > PTP_PIN_TOD_SEC_MSB,
> > > PTP_PIN_TOD_SEC_LSB,
> > > PTP_PIN_TOD_NSEC,
> > > + PTP_PIN_WF_HIGH_PERIOD,
> > > + PTP_PIN_WF_LOW_PERIOD,
> > > PTP_CFG_MISC,
> > > PTP_CLK_CFG_ADJ_CFG,
> > > PTP_CLK_CFG_ADJ_FREQ,
> > > --
> > > 2.7.4
> > >
> >
> > Thanks,
> > -Vladimir
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