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Date:   Thu, 26 Dec 2019 20:01:00 +0100
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     andrew@...n.ch, f.fainelli@...il.com, davem@...emloft.net,
        netdev@...r.kernel.org, linux-amlogic@...ts.infradead.org
Cc:     linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Subject: [PATCH v2 0/1] dwmac-meson8b: Ethernet RGMII TX delay fix

The Ethernet TX performance has been historically bad on Meson8b and
Meson8m2 SoCs because high packet loss was seen. Today I (presumably)
found out why this is: the input clock (which feeds the RGMII TX clock)
has to be at least 4 times 125MHz. With the fixed "divide by 2" in the
clock tree this means that m250_div needs to be at least 2.

With this patch and a 2ns TX delay generated by either the MAC *or* the
PHY this results in improved Ethernet TX performance and no packet loss
anymore:
# iperf3 -c 192.168.1.100
Connecting to host 192.168.1.100, port 5201
[  5] local 192.168.1.163 port 42636 connected to 192.168.1.100 port 5201
[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
[  5]   0.00-1.00   sec   105 MBytes   878 Mbits/sec    0    609 KBytes       
[  5]   1.00-2.00   sec   106 MBytes   885 Mbits/sec    0    683 KBytes       
[  5]   2.00-3.09   sec  73.7 MBytes   570 Mbits/sec    0    683 KBytes       
[  5]   3.09-4.00   sec  81.9 MBytes   754 Mbits/sec    0    795 KBytes       
[  5]   4.00-5.00   sec   104 MBytes   869 Mbits/sec    0    877 KBytes       
[  5]   5.00-6.00   sec   105 MBytes   878 Mbits/sec    0    877 KBytes       
[  5]   6.00-7.00   sec  68.0 MBytes   571 Mbits/sec    0    877 KBytes       
[  5]   7.00-8.00   sec  80.7 MBytes   676 Mbits/sec    0    877 KBytes       
[  5]   8.00-9.01   sec   102 MBytes   853 Mbits/sec    0    877 KBytes       
[  5]   9.01-10.00  sec   101 MBytes   859 Mbits/sec    0    877 KBytes       
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-10.00  sec   927 MBytes   778 Mbits/sec    0             sender
[  5]   0.00-10.01  sec   927 MBytes   777 Mbits/sec                  receiver


The .dts of these boards are still using an incorrect TX delay of 4ns.
This will be fixed in follow-up patches when it's clear whether the MAC
really generates an RX delay and how this can be configured.


Changes since v1 [0]:
- update cover-letter title
- dropped the .dts patches after discussion with Andrew in [1]
- slightly reworded the patch description of patch #1 to indicate that
  the goal is to fix the TX delay generated by the MAC, without
  suggesting that it's recommended to let the MAC actually generate it.


[0] https://patchwork.kernel.org/cover/11309887/
[1] https://patchwork.kernel.org/patch/11309891/


Martin Blumenstingl (1):
  net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs

 .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c    | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

-- 
2.24.1

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