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Date: Thu, 26 Dec 2019 12:54:42 -0800 From: Florian Fainelli <f.fainelli@...il.com> To: Martin Blumenstingl <martin.blumenstingl@...glemail.com>, andrew@...n.ch, davem@...emloft.net, netdev@...r.kernel.org, linux-amlogic@...ts.infradead.org Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH 1/2] net: phy: realtek: add logging for the RGMII TX delay configuration On 12/26/2019 10:51 AM, Martin Blumenstingl wrote: > RGMII requires a delay of 2ns between the data and the clock signal. > There are at least three ways this can happen. One possibility is by > having the PHY generate this delay. > This is a common source for problems (for example with slow TX speeds or > packet loss when sending data). The TX delay configuration of the > RTL8211F PHY can be set either by pin-strappping the RXD1 pin (HIGH > means enabled, LOW means disabled) or through configuring a paged > register. The setting from the RXD1 pin is also reflected in the > register. > > Add debug logging to the TX delay configuration on RTL8211F so it's > easier to spot these issues (for example if the TX delay is enabled for > both, the RTL8211F PHY and the MAC). > This is especially helpful because there is no public datasheet for the > RTL8211F PHY available with all the RX/TX delay specifics. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com> Reviewed-by: Florian Fainelli <f.fainelli@...il.com> -- Florian
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