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Date: Fri, 27 Dec 2019 16:33:48 -0800 (PST) From: David Miller <davem@...emloft.net> To: martin.blumenstingl@...glemail.com Cc: linux-amlogic@...ts.infradead.org, netdev@...r.kernel.org, khilman@...libre.com, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, balbes-150@...dex.ru, ingrassia@...genesys.com, jbrunet@...libre.com, linus.luessing@...3.blue Subject: Re: [PATCH 0/3] Meson8b/8m2: Ethernet RGMII TX delay fixes From: Martin Blumenstingl <martin.blumenstingl@...glemail.com> Date: Wed, 25 Dec 2019 01:56:52 +0100 > The Ethernet TX performance has been historically bad on Meson8b and > Meson8m2 SoCs because high packet loss was seen. Today I (presumably) > found out why this is: the input clock (which feeds the RGMII TX clock) > has to be at least 4 times 125MHz. With the fixed "divide by 2" in the > clock tree this means that m250_div needs to be at least 2. ... It looks there needs to be more discussion on this series, please respin once the discussions are resolved. Thank you.
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