netdev - Re: [PATCH] net: mlx5: Use writeX() to ring doorbell and remove reduntant wmb()

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Message-Id: <EFADA53B-CB84-44E2-922B-83C505D4AE8B@oracle.com>
Date:   Fri, 3 Jan 2020 18:42:59 +0200
From:   Liran Alon <liran.alon@...cle.com>
To:     Jason Gunthorpe <jgg@...pe.ca>
Cc:     Will Deacon <will@...nel.org>, saeedm@...lanox.com,
        leon@...nel.org, netdev@...r.kernel.org,
        linux-rdma@...r.kernel.org, eli@...lanox.com, tariqt@...lanox.com,
        danielm@...lanox.com,
        Håkon Bugge <haakon.bugge@...cle.com>
Subject: Re: [PATCH] net: mlx5: Use writeX() to ring doorbell and remove
 reduntant wmb()

> On 3 Jan 2020, at 18:36, Jason Gunthorpe <jgg@...pe.ca> wrote:
> 
> On Fri, Jan 03, 2020 at 06:31:18PM +0200, Liran Alon wrote:
> 
>>> I am surprised that AMD is different here, the evolution of the WC
>>> feature on x86 was to transparently speed up graphics, so I'm pretty
>>> surprised AMD can get away with not ordering the same as Intel..
>> 
>> Completely agree. I was very surprised to see this from AMD SDM and
>> Optimization Guide SDM.  It made sense to me too that graphics frame
>> buffer is written to WC memory and then is committed to GPU by
>> writing to some doorbell register mapped as UC memory.
> 
> It is possible this manual is wrong or misleading?
> 
> Having WC writes not strongly order after UC writes to the same
> device, on x86, seems very, very surprising to me. Everything is
> ordered on x86 :)
> 
> Jason

I thought so the same at first. This is why I checked both AMD SDM and AMD Optimisation Guide
and made sure to quote relevant section this document. I will be glad to be corrected that’s solely
a mistake. But it seems very intentional and explicitly documented in multiple places.

Also note that WC memory is considered weakly-ordered in x86. E.g. non-temporal stores that
appear in program order after a previous store to WB memory, can complete before the store to
WB memory. In addition, a store to WC memory is considered complete once the stored data reach
the WC buffer, where it’s not globally visible. In contrast to stores to WB/UC memory that are globally
visible once they are complete (In contrast to retired).

But again, I agree this is very surprising and unexpected… To have a single arch have different caching
behaviour that needs to be considered based on CPU vendor...

-Liran