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Date:   Sat, 4 Jan 2020 19:59:37 -0800
From:   Chris Healy <cphealy@...il.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     David Miller <davem@...emloft.net>,
        netdev <netdev@...r.kernel.org>,
        Vivien Didelot <vivien.didelot@...il.com>
Subject: Re: [PATCH net v2] net: dsa: mv88e6xxx: Preserve priority when
 setting CPU port.

Tested-by: Chris Healy <cphealy@...il.com>

On Sat, Jan 4, 2020 at 2:14 PM Andrew Lunn <andrew@...n.ch> wrote:
>
> The 6390 family uses an extended register to set the port connected to
> the CPU. The lower 5 bits indicate the port, the upper three bits are
> the priority of the frames as they pass through the switch, what
> egress queue they should use, etc. Since frames being set to the CPU
> are typically management frames, BPDU, IGMP, ARP, etc set the priority
> to 7, the reset default, and the highest.
>
> Fixes: 33641994a676 ("net: dsa: mv88e6xxx: Monitor and Management tables")
> Signed-off-by: Andrew Lunn <andrew@...n.ch>
>
> ---
> v2: Fix a couple of spelling errors.
> ---
>  drivers/net/dsa/mv88e6xxx/global1.c | 5 +++++
>  drivers/net/dsa/mv88e6xxx/global1.h | 1 +
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
> index 120a65d3e3ef..b016cc205f81 100644
> --- a/drivers/net/dsa/mv88e6xxx/global1.c
> +++ b/drivers/net/dsa/mv88e6xxx/global1.c
> @@ -360,6 +360,11 @@ int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
>  {
>         u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
>
> +       /* Use the default high priority for management frames sent to
> +        * the CPU.
> +        */
> +       port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
> +
>         return mv88e6390_g1_monitor_write(chip, ptr, port);
>  }
>
> diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
> index bc5a6b2bb1e4..5324c6f4ae90 100644
> --- a/drivers/net/dsa/mv88e6xxx/global1.h
> +++ b/drivers/net/dsa/mv88e6xxx/global1.h
> @@ -211,6 +211,7 @@
>  #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST         0x2000
>  #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST          0x2100
>  #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST             0x3000
> +#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI     0x00e0
>  #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK                        0x00ff
>
>  /* Offset 0x1C: Global Control 2 */
> --
> 2.24.0
>

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