netdev - Re: [PATCH v4 net-next 0/9] Convert Felix DSA switch to PHYLINK

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Date:   Sun, 05 Jan 2020 15:05:00 -0800 (PST)
From:   David Miller <davem@...emloft.net>
To:     olteanv@...il.com
Cc:     jakub.kicinski@...ronome.com, linux@...linux.org.uk,
        andrew@...n.ch, f.fainelli@...il.com, vivien.didelot@...il.com,
        alexandru.marginean@....com, claudiu.manoil@....com,
        xiaoliang.yang_1@....com, yangbo.lu@....com,
        netdev@...r.kernel.org, alexandre.belloni@...tlin.com,
        horatiu.vultur@...rochip.com, UNGLinuxDriver@...rochip.com,
        vladimir.oltean@....com
Subject: Re: [PATCH v4 net-next 0/9] Convert Felix DSA switch to PHYLINK

From: David Miller <davem@...emloft.net>
Date: Sun, 05 Jan 2020 14:56:20 -0800 (PST)

> From: Vladimir Oltean <olteanv@...il.com>
> Date: Fri,  3 Jan 2020 22:01:18 +0200
> 
>> Unlike most other conversions, this one is not by far a trivial one, and should
>> be seen as "Layerscape PCS meets PHYLINK". Actually, the PCS doesn't
>> need a lot of hand-holding and most of our other devices 'just work'
>> (this one included) without any sort of operating system awareness, just
>> an initialization procedure done typically in the bootloader.
>> Our issues start when the PCS stops from "just working", and that is
>> where PHYLINK comes in handy.
>> 
>> The PCS is not specific to the Vitesse / Microsemi / Microchip switching core
>> at all. Variations of this SerDes/PCS design can also be found on DPAA1 and
>> DPAA2 hardware.
>> 
>> The main idea of the abstraction provided is that the PCS looks so much like a
>> PHY device, that we model it as an actual PHY device and run the generic PHY
>> functions on it, where appropriate.
>  ...
> 
> Series applied, please address any follow-up feedback you receive.

Actually I reverted, please fix this warning and resubmit:

drivers/net/dsa/ocelot/felix.c: In function ‘felix_phylink_mac_config’:
drivers/net/dsa/ocelot/felix.c:210:22: warning: unused variable ‘ocelot_port’ [-Wunused-variable]
  struct ocelot_port *ocelot_port = ocelot->ports[port];
                      ^~~~~~~~~~~

Thank you.