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Date:   Wed, 8 Jan 2020 13:47:48 +0100
From:   Arnd Bergmann <>
To:     Vladimir Oltean <>
Cc:     David Miller <>,
        Jakub Kicinski <>,
        Russell King - ARM Linux <>,
        Andrew Lunn <>,
        Florian Fainelli <>,
        Vivien Didelot <>,,
        Claudiu Manoil <>,, yangbo lu <>,
        Networking <>,
        Alexandre Belloni <>,,,
        Vladimir Oltean <>
Subject: Re: [PATCH v5 net-next 9/9] net: dsa: felix: Add PCS operations for PHYLINK

On Mon, Jan 6, 2020 at 2:37 AM Vladimir Oltean <> wrote:
> From: Vladimir Oltean <>
> Layerscape SoCs traditionally expose the SerDes configuration/status for
> Ethernet protocols (PCS for SGMII/USXGMII/10GBase-R etc etc) in a register
> format that is compatible with clause 22 or clause 45 (depending on
> SerDes protocol). Each MAC has its own internal MDIO bus on which there
> is one or more of these PCS's, responding to commands at a configurable
> PHY address. The per-port internal MDIO bus (which is just for PCSs) is
> totally separate and has nothing to do with the dedicated external MDIO
> controller (which is just for PHYs), but the register map for the MDIO
> controller is the same.

I get randconfig build failures after this patch:

drivers/net/dsa/ocelot/felix_vsc9959.o: In function `vsc9959_mdio_bus_alloc':
felix_vsc9959.c:(.text+0x19c): undefined reference to `enetc_hw_alloc'
felix_vsc9959.c:(.text+0x1d1): undefined reference to `enetc_mdio_read'
felix_vsc9959.c:(.text+0x1d8): undefined reference to `enetc_mdio_write'

I'll send a patch after a bit more testing


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