netdev - Re: [PATCH net-next RFC 3/3] net/mlx5: Add FW upgrade reset support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <3fd6912b-ec94-195f-5996-8f0d505eec64@mellanox.com>
Date:   Sat, 18 Jan 2020 19:57:37 +0000
From:   Moshe Shemesh <moshe@...lanox.com>
To:     Jakub Kicinski <kuba@...nel.org>
CC:     "David S. Miller" <davem@...emloft.net>,
        Alexander Duyck <alexander.duyck@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH net-next RFC 3/3] net/mlx5: Add FW upgrade reset support


On 1/17/2020 3:26 AM, Jakub Kicinski wrote:
> On Thu, 16 Jan 2020 14:52:35 +0000, Moshe Shemesh wrote:
>>> If multiple devices under one bridge are a real concern (or otherwise
>>> interdependencies) would it make sense to mark the devices as "reload
>>> pending" and perform the reloads once all devices in the group has this
>>> mark set?
>> All mlx5 current devices support PCI - Express only.
>>
>> PCI-Express device should have its own PCI-Express bridge, it is 1x1
>> connection.
>>
>> So the check here is just to verify, all functions found under the
>> bridge are expected to be the same device functions (PFs and VFs).
> Ah, good, I couldn't confirm that PCIe fact with google fast enough :)
> The check sounds good then, with perhaps a small suggestion to add
> a helper in PCIe core if it's already done by two drivers? Can be as
> a follow up..

OK, we will follow up.

We are preparing larger series for FW upgrade reset that relies on this RFC.

Such shared function should go to pcie subsystem, we will follow up with 
it for both drivers once the full mlx5 solution is upstream.