netdev - Re: [EXT] Re: [PATCH] bus: fsl-mc: Add ACPI support for fsl-mc

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Message-ID: <20200201114919.GQ25745@shell.armlinux.org.uk>
Date:   Sat, 1 Feb 2020 11:49:19 +0000
From:   Russell King - ARM Linux admin <linux@...linux.org.uk>
To:     Jakub Kicinski <kuba@...nel.org>, Jiri Pirko <jiri@...lanox.com>
Cc:     Andrew Lunn <andrew@...n.ch>, Robin Murphy <robin.murphy@....com>,
        Calvin Johnson <calvin.johnson@....com>, stuyoder@...il.com,
        nleeder@...eaurora.org, Ioana Ciornei <ioana.ciornei@....com>,
        Cristi Sovaiala <cristian.sovaiala@....com>,
        Hanjun Guo <guohanjun@...wei.com>,
        Will Deacon <will@...nel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Marc Zyngier <maz@...nel.org>,
        Pankaj Bansal <pankaj.bansal@....com>,
        Jon Nettleton <jon@...id-run.com>,
        ACPI Devel Maling List <linux-acpi@...r.kernel.org>,
        Len Brown <lenb@...nel.org>,
        Jason Cooper <jason@...edaemon.net>,
        Andy Wang <Andy.Wang@....com>,
        Makarand Pawagi <makarand.pawagi@....com>,
        Varun Sethi <V.Sethi@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Laurentiu Tudor <laurentiu.tudor@....com>,
        Paul Yang <Paul.Yang@....com>,
        Ard Biesheuvel <ard.biesheuvel@...aro.org>,
        "<netdev@...r.kernel.org>" <netdev@...r.kernel.org>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Shameerali Kolothum Thodi 
        <shameerali.kolothum.thodi@...wei.com>,
        Sudeep Holla <sudeep.holla@....com>
Subject: Re: [EXT] Re: [PATCH] bus: fsl-mc: Add ACPI support for fsl-mc

On Fri, Jan 31, 2020 at 07:40:50AM -0800, Jakub Kicinski wrote:
> On Fri, 31 Jan 2020 15:15:00 +0000, Russell King - ARM Linux admin
> wrote:
> > I have some prototype implementation for driving the QSFP+ cage, but
> > I haven't yet worked out how to sensible deal with the "is it 4x 10G
> > or 1x 40G" issue you mention above, and how to interface the QSFP+
> > driver sensibly with one or four network drivers.
> 
> I'm pretty sure you know this but just FWIW - vendors who do it in FW
> write the current config down in NVM so it doesn't get affected by
> reboots and use devlink port splitting to change it.

+Jiri

I wasn't aware of devlink port splitting, so thanks for that. However,
it could do with some better documentation - there's nothing on it
afaics in the Documentation subdirectory, and "man devlink-port"
doesn't give much away either:

   devlink port split - split devlink port into more
       DEV/PORT_INDEX - specifies the devlink port to operate on.

       count COUNT
              number of ports to split to.

It's the "into more" that's not clear - presumably more ports, and
presumably each port is a network device, but this isn't explained.

I think what this is trying to say is that, if we have a QSFP+ cage
with 4 serdes lines running at 10G, and they are initially treated as
a single 40G ethernet:

	devlink port split device/1 count 4

will then give us four 10G network devices, and:

	devlink port unsplit device/1

will recombine them back to a single 40G network device.

What if someone decides to do:

	devlink port split device/1 count 2

what do we end up with?  Presumably two network devices running with
two serdes lanes each (if supported by the hardware).  At that point
can they then do:

	devlink port split device/2 count 2

and end up with one network device with two 10G serdes lanes, and two
network devices each with one 10G serdes lane, or can port splitting
only be used on the "master" device/port ?

Unfortunately, I don't think I have any network devices that support
this so I can't experiment to find out how this should work; yes, I
have a Mellanox card, but it supports a single 10G SFP+, and therefore
does not support port splitting.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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