netdev - [for-next PATCH 2/5] dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc

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Message-ID: <20200222120358.10003-3-grygorii.strashko@ti.com>
Date:   Sat, 22 Feb 2020 14:03:55 +0200
From:   Grygorii Strashko <grygorii.strashko@...com>
To:     Kishon Vijay Abraham I <kishon@...com>,
        Tero Kristo <t-kristo@...com>,
        "David S. Miller" <davem@...emloft.net>
CC:     <netdev@...r.kernel.org>, Sekhar Nori <nsekhar@...com>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Grygorii Strashko <grygorii.strashko@...com>
Subject: [for-next PATCH 2/5] dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc

TI AM654x/J721E SoCs have the same PHY interface selection mechanism for
CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields
placement is different.

This patch adds corresponding compatible strings to enable support for TI
AM654x/J721E SoCs.

Signed-off-by: Grygorii Strashko <grygorii.strashko@...com>
---
 Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt
index 50ce9ae0f7a5..83b78c1c0644 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt
@@ -40,6 +40,7 @@ Required properties:
 			  "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform
 			  "ti,am43xx-phy-gmii-sel" for am43xx platform
 			  "ti,dm814-phy-gmii-sel" for dm814x platform
+			  "ti,am654-phy-gmii-sel" for AM654x/J721E platform
 - reg			: Address and length of the register set for the device
 - #phy-cells		: must be 2.
 			  cell 1 - CPSW port number (starting from 1)
-- 
2.17.1