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Date:   Wed,  4 Mar 2020 21:02:03 -0800
From:   Luke Nelson <lukenels@...washington.edu>
To:     bpf@...r.kernel.org
Cc:     Luke Nelson <luke.r.nels@...il.com>,
        Jonathan Corbet <corbet@....net>,
        Alexei Starovoitov <ast@...nel.org>,
        Daniel Borkmann <daniel@...earbox.net>,
        Martin KaFai Lau <kafai@...com>,
        Song Liu <songliubraving@...com>, Yonghong Song <yhs@...com>,
        Andrii Nakryiko <andriin@...com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Björn Töpel <bjorn.topel@...il.com>,
        Xi Wang <xi.wang@...il.com>,
        Mauro Carvalho Chehab <mchehab+samsung@...nel.org>,
        Stephen Hemminger <stephen@...workplumber.org>,
        Rob Herring <robh@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jonathan Cameron <Jonathan.Cameron@...wei.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
        netdev@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: [PATCH bpf-next v5 0/4] eBPF JIT for RV32G

This series adds an eBPF JIT for 32-bit RISC-V (RV32G) to the kernel,
adapted from the RV64 JIT and the 32-bit ARM JIT.

There are two main changes required for this to work compared to
the RV64 JIT.

First, eBPF registers are 64-bit, while RV32G registers are 32-bit.
BPF registers either map directly to 2 RISC-V registers, or reside
in stack scratch space and are saved and restored when used.

Second, many 64-bit ALU operations do not trivially map to 32-bit
operations. Operations that move bits between high and low words,
such as ADD, LSH, MUL, and others must emulate the 64-bit behavior
in terms of 32-bit instructions.

Supported features:

The RV32 JIT supports the same features and instructions as the
RV64 JIT, with the following exceptions:

- ALU64 DIV/MOD: Requires loops to implement on 32-bit hardware.

- BPF_XADD | BPF_DW: There's no 8-byte atomic instruction in RV32.

These features are also unsupported on other BPF JITs for 32-bit
architectures.

Testing:

- lib/test_bpf.c
test_bpf: Summary: 378 PASSED, 0 FAILED, [349/366 JIT'ed]
test_bpf: test_skb_segment: Summary: 2 PASSED, 0 FAILED

The tests that are not JITed are all due to use of 64-bit div/mod
or 64-bit xadd.

- tools/testing/selftests/bpf/test_verifier.c
Summary: 1415 PASSED, 122 SKIPPED, 43 FAILED

Tested both with and without BPF JIT hardening.

This is the same set of tests that pass using the BPF interpreter
with the JIT disabled.

Running the BPF kernel tests / selftests on riscv32 is non-trivial,
to help others reproduce the test results I made a guide here:
https://github.com/lukenels/meta-linux-utils/tree/master/rv32-linux

Verification and synthesis:

We developed the RV32 JIT using our automated verification tool,
Serval. We have used Serval in the past to verify patches to the
RV64 JIT. We also used Serval to superoptimize the resulting code
through program synthesis.

You can find the tool and a guide to the approach and results here:
https://github.com/uw-unsat/serval-bpf/tree/rv32-jit-v5

Thanks again for all the comments!

Changelog:

v4 -> v5:
  * Factored common code (build_body, bpf_int_jit_compile, etc)
    to bpf_jit_core.c (Björn Töpel).
  * Moved RV32-specific changes to bpf_jit.h from patch 1 to patch 2
    (Björn Töpel).
  * Removed "_rv32_" from function names in JIT as it is
    redundant (Björn Töpel).
  * Added commit message to MAINTAINERS and made sure to keep
    entries in order (Andy Shevchenko).

v3 -> v4:
  * Added more comments and cleaned up style nits (Björn Töpel).
  * Factored common code in RV64 and RV32 JITs into a separate header
    (Song Liu, Björn Töpel).
  * Added an optimization in the BPF_ALU64 BPF_ADD BPF_X case.
  * Updated MAINTAINERS and kernel documentation (Björn Töpel).

v2 -> v3:
  * Added support for far jumps / branches similar to RV64 JIT.
  * Added support for tail calls.
  * Cleaned up code with more optimizations and comments.
  * Removed special zero-extension instruction from BPF_ALU64
    case (Jiong Wang).

v1 -> v2:
  * Added support for far conditional branches.
  * Added the zero-extension optimization (Jiong Wang).
  * Added more optimizations for operations with an immediate operand.

Luke Nelson (4):
  riscv, bpf: factor common RISC-V JIT code
  riscv, bpf: add RV32G eBPF JIT
  bpf, doc: add BPF JIT for RV32G to BPF documentation
  MAINTAINERS: add entry for RV32G BPF JIT

 Documentation/admin-guide/sysctl/net.rst      |    3 +-
 Documentation/networking/filter.txt           |    2 +-
 MAINTAINERS                                   |   13 +-
 arch/riscv/Kconfig                            |    2 +-
 arch/riscv/net/Makefile                       |    9 +-
 arch/riscv/net/bpf_jit.h                      |  514 +++++++
 arch/riscv/net/bpf_jit_comp32.c               | 1310 +++++++++++++++++
 .../net/{bpf_jit_comp.c => bpf_jit_comp64.c}  |  605 +-------
 arch/riscv/net/bpf_jit_core.c                 |  166 +++
 9 files changed, 2018 insertions(+), 606 deletions(-)
 create mode 100644 arch/riscv/net/bpf_jit.h
 create mode 100644 arch/riscv/net/bpf_jit_comp32.c
 rename arch/riscv/net/{bpf_jit_comp.c => bpf_jit_comp64.c} (69%)
 create mode 100644 arch/riscv/net/bpf_jit_core.c

Cc: Jonathan Corbet <corbet@....net>
Cc: Alexei Starovoitov <ast@...nel.org>
Cc: Daniel Borkmann <daniel@...earbox.net>
Cc: Martin KaFai Lau <kafai@...com>
Cc: Song Liu <songliubraving@...com>
Cc: Yonghong Song <yhs@...com>
Cc: Andrii Nakryiko <andriin@...com>
Cc: "David S. Miller" <davem@...emloft.net>
Cc: Jakub Kicinski <kuba@...nel.org>
Cc: Paul Walmsley <paul.walmsley@...ive.com>
Cc: Palmer Dabbelt <palmer@...belt.com>
Cc: Albert Ou <aou@...s.berkeley.edu>
Cc: "Björn Töpel" <bjorn.topel@...il.com>
Cc: Luke Nelson <luke.r.nels@...il.com>
Cc: Xi Wang <xi.wang@...il.com>
Cc: Mauro Carvalho Chehab <mchehab+samsung@...nel.org>
Cc: Stephen Hemminger <stephen@...workplumber.org>
Cc: Rob Herring <robh@...nel.org>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Jonathan Cameron <Jonathan.Cameron@...wei.com>
Cc: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc: linux-doc@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: netdev@...r.kernel.org
Cc: bpf@...r.kernel.org
Cc: linux-riscv@...ts.infradead.org

-- 
2.20.1

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