netdev - Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock

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Message-ID: <158470229183.43774.8932556125293087780@kwain>
Date:   Fri, 20 Mar 2020 12:04:53 +0100
From:   Antoine Tenart <antoine.tenart@...tlin.com>
To:     Andrew Lunn <andrew@...n.ch>, Vladimir Oltean <olteanv@...il.com>
Cc:     "David S. Miller" <davem@...emloft.net>,
        netdev <netdev@...r.kernel.org>,
        Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>
Subject: Re: [PATCH net-next 1/4] net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

Hello,

Quoting Vladimir Oltean (2020-03-20 11:38:05)
> On Fri, 20 Mar 2020 at 12:09, Andrew Lunn <andrew@...n.ch> wrote:
> >
> > On Thu, Mar 19, 2020 at 11:16:46PM +0200, Vladimir Oltean wrote:
> > > From: Vladimir Oltean <vladimir.oltean@....com>
> > >
> > > There is nothing RX-specific about these clock skew values. So remove
> > > "RX" from the name in preparation for the next patch where TX delays are
> > > also going to be configured.
> > >
> > > Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
> > > ---
> > >  drivers/net/phy/mscc/mscc.h      | 18 +++++++++---------
> > >  drivers/net/phy/mscc/mscc_main.c |  2 +-
> > >  2 files changed, 10 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h
> > > index 29ccb2c9c095..56feb14838f3 100644
> > > --- a/drivers/net/phy/mscc/mscc.h
> > > +++ b/drivers/net/phy/mscc/mscc.h
> > > @@ -12,15 +12,15 @@
> > >  #include "mscc_macsec.h"
> > >  #endif
> > >
> > > -enum rgmii_rx_clock_delay {
> > > -     RGMII_RX_CLK_DELAY_0_2_NS = 0,
> > > -     RGMII_RX_CLK_DELAY_0_8_NS = 1,
> > > -     RGMII_RX_CLK_DELAY_1_1_NS = 2,
> > > -     RGMII_RX_CLK_DELAY_1_7_NS = 3,
> > > -     RGMII_RX_CLK_DELAY_2_0_NS = 4,
> > > -     RGMII_RX_CLK_DELAY_2_3_NS = 5,
> > > -     RGMII_RX_CLK_DELAY_2_6_NS = 6,
> > > -     RGMII_RX_CLK_DELAY_3_4_NS = 7
> > > +enum rgmii_clock_delay {
> > > +     RGMII_CLK_DELAY_0_2_NS = 0,
> > > +     RGMII_CLK_DELAY_0_8_NS = 1,
> > > +     RGMII_CLK_DELAY_1_1_NS = 2,
> > > +     RGMII_CLK_DELAY_1_7_NS = 3,
> > > +     RGMII_CLK_DELAY_2_0_NS = 4,
> > > +     RGMII_CLK_DELAY_2_3_NS = 5,
> > > +     RGMII_CLK_DELAY_2_6_NS = 6,
> > > +     RGMII_CLK_DELAY_3_4_NS = 7
> > >  };
> >
> > Can this be shared?
> >
> > https://www.spinics.net/lists/netdev/msg638747.html
> >
> > Looks to be the same values?
> >
> > Can some of the implementation be consolidated?

> - That patch is writing to MSCC_PHY_RGMII_SETTINGS (defined to 18).
> This one is writing to MSCC_PHY_RGMII_CNTL (defined to 20). And since
> I have no documentation to understand why, I'm back to square 1.

These are two different registers, using similar values. I guess the
register was moved around as those PHYs are from the same family; but
I'm not sure if it's correct to consolidate it as we do not know for
sure. (Practically speaking the same values are used, so why not).

Thanks,
Antoine

-- 
Antoine Ténart, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com