netdev - Re: [PATCH net] net: phy: microchip_t1: add lan87xx_phy

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Date:   Sat, 21 Mar 2020 20:12:23 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     yuiko.oshino@...rochip.com
Cc:     davem@...emloft.net, UNGLinuxDriver@...rochip.com,
        netdev@...r.kernel.org
Subject: Re: [PATCH net] net: phy: microchip_t1: add lan87xx_phy_init to
 initialize the lan87xx phy.

From: Yuiko Oshino <yuiko.oshino@...rochip.com>
Date: Tue, 17 Mar 2020 15:08:38 -0400

> lan87xx_phy_init() initializes the lan87xx phy.
> 
> fixes: 3e50d2da5850 ("Add driver for Microchip LAN87XX T1 PHYs")
> Signed-off-by: Yuiko Oshino <yuiko.oshino@...rochip.com>

"Fixes: " should be capitalized.

You commit message is way too terse.

> +	static const struct access_ereg_val init[] = {
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE, 0x0B, 0x000A},
> +		{PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC, 0x8, 0},
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x8, 0},
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x10, 0x0009},
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 0x17, 0},
> +		/* TC10 Config */
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x20, 0x0023},
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_PCS, 0x20, 0x3C3C},
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x21, 0x274F},
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x20, 0x80A7},
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x24, 0x9110},
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_MISC, 0x20, 0x0087},
> +		/* HW Init */
> +		{PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI, 0x1A, 0x0300},
> +	};

What do these registers do, and what do the values programmed into them
do?

If you don't know, how can you know if this code is correct?

You must document this as much as possible.

Thank you.