netdev - Re: [PATCH 4/5] net: macb: WoL support for GEM type of Ethernet controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6fc99e01-6d64-4248-3627-aa14a914df72@gmail.com>
Date:   Thu, 16 Apr 2020 12:25:24 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     nicolas.ferre@...rochip.com, linux-arm-kernel@...ts.infradead.org,
        netdev@...r.kernel.org,
        Claudiu Beznea <claudiu.beznea@...rochip.com>,
        harini.katakam@...inx.com
Cc:     linux-kernel@...r.kernel.org,
        "David S. Miller" <davem@...emloft.net>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        pthombar@...ence.com, sergio.prado@...abworks.com,
        antoine.tenart@...tlin.com, linux@...linux.org.uk, andrew@...n.ch,
        michal.simek@...inx.com
Subject: Re: [PATCH 4/5] net: macb: WoL support for GEM type of Ethernet
 controller



On 4/16/2020 10:44 AM, nicolas.ferre@...rochip.com wrote:
> From: Nicolas Ferre <nicolas.ferre@...rochip.com>
> 
> Adapt the Wake-on-Lan feature to the Cadence GEM Ethernet controller.
> This controller has different register layout and cannot be handled by
> previous code.
> We disable completely interrupts on all the queues but the queue 0.
> Handling of WoL interrupt is done in another interrupt handler
> positioned depending on the controller version used, just between
> suspend() and resume() calls.
> It allows to lower pressure on the generic interrupt hot path by
> removing the need to handle 2 tests for each IRQ: the first figuring out
> the controller revision, the second for actually knowing if the WoL bit
> is set.
> 
> Queue management in suspend()/resume() functions inspired from RFC patch
> by Harini Katakam <harinik@...inx.com>, thanks!
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre@...rochip.com>
> ---

[snip]

>   
> +static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
> +{
> +	struct macb_queue *queue = dev_id;
> +	struct macb *bp = queue->bp;
> +	u32 status;
> +
> +	status = queue_readl(queue, ISR);
> +
> +	if (unlikely(!status))
> +		return IRQ_NONE;
> +
> +	spin_lock(&bp->lock);
> +
> +	if (status & GEM_BIT(WOL)) {
> +		queue_writel(queue, IDR, GEM_BIT(WOL));
> +		gem_writel(bp, WOL, 0);
> +		netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
> +			    (unsigned int)(queue - bp->queues),
> +			    (unsigned long)status);
> +		if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> +			queue_writel(queue, ISR, GEM_BIT(WOL));

You would also need a pm_wakeup_event() call here to record that this 
device did wake-up the system.
-- 
Florian