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Message-ID: <VI1PR04MB6941C603529307039AF7F4ABEEAF0@VI1PR04MB6941.eurprd04.prod.outlook.com>
Date:   Mon, 27 Apr 2020 20:00:28 +0000
From:   Leonard Crestez <leonard.crestez@....com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     Andy Duan <fugang.duan@....com>,
        David Miller <davem@...emloft.net>,
        netdev <netdev@...r.kernel.org>,
        Chris Healy <Chris.Healy@....aero>,
        dl-linux-imx <linux-imx@....com>, Chris Healy <cphealy@...il.com>
Subject: Re: [PATCH] net: ethernet: fec: Replace interrupt driven MDIO with
 polled IO

On 2020-04-27 7:46 PM, Andrew Lunn wrote:
> On Mon, Apr 27, 2020 at 03:19:54PM +0000, Leonard Crestez wrote:
>> Hello,
>>
>> This patch breaks network boot on at least imx8mm-evk. Boot works if I
>> revert just commit 29ae6bd1b0d8 ("net: ethernet: fec: Replace interrupt
>> driven MDIO with polled IO") on top of next-20200424.
> 
> Hi Leonard
> 
> Please could you try this:
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> index 951e14a3de0e..3c1adaf7affa 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> @@ -109,6 +109,7 @@ &fec1 {
>          phy-handle = <&ethphy0>;
>          phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
>          phy-reset-duration = <10>;
> +       phy-reset-post-delay = <100>;
>          fsl,magic-packet;
>          status = "okay";
> 
> 
> There is an interesting post from Fabio Estevam
> 
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fu-boot.denx.narkive.com%2FPlutD3Rg%2Fpatch-1-3-phy-atheros-use-ar8035-config-for-ar8031&amp;data=02%7C01%7Cleonard.crestez%40nxp.com%7C6e84d8adeb644c51a86408d7eaca858d%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637236027867051637&amp;sdata=s7825L%2BHQV%2FmPR2saYHcoSAgVTlZDr5gYT62kVgdeJA%3D&amp;reserved=0
> 
> Thanks
> 	Andrew
> 

Does not help. What does seem to help is inserting prints after the 
FEC_ENET_MII check but that's probably because it inject a long delay 
equivalent to the long udelay Andy has mentioned.

I found that in my case FEC_ENET_MII is already set on entry to 
fec_enet_mdio_read, doesn't this make fec_enet_mdio_wait pointless?

Perhaps the problem is that the MII Interrupt pending bit is not 
cleared. I can fix the problem like this:

diff --git drivers/net/ethernet/freescale/fec_main.c 
drivers/net/ethernet/freescale/fec_main.c
index 1ae075a246a3..f1330071647c 100644
--- drivers/net/ethernet/freescale/fec_main.c
+++ drivers/net/ethernet/freescale/fec_main.c
@@ -1841,10 +1841,19 @@ static int fec_enet_mdio_read(struct mii_bus 
*bus, int mii_id, int regnum)

         ret = pm_runtime_get_sync(dev);
         if (ret < 0)
                 return ret;

+       if (1) {
+               u32 ievent;
+               ievent = readl(fep->hwp + FEC_IEVENT);
+               if (ievent & FEC_ENET_MII) {
+                       dev_warn(dev, "found FEC_ENET_MII pending\n");
+                       writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
+               }
+       }
+
         if (is_c45) {
                 frame_start = FEC_MMFR_ST_C45;

                 /* write address */
                 frame_addr = (regnum >> 16);


--
Regards,
Leonard

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