lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 6 May 2020 12:58:28 -0700
From:   Richard Cochran <>
To:     Vladimir Oltean <>
Subject: Re: [PATCH net] net: dsa: sja1105: the PTP_CLK extts input reacts on
 both edges

On Wed, May 06, 2020 at 08:48:13PM +0300, Vladimir Oltean wrote:
> From: Vladimir Oltean <>
> It looks like the sja1105 external timestamping input is not as generic
> as we thought. When fed a signal with 50% duty cycle, it will timestamp
> both the rising and the falling edge. When fed a short pulse signal,
> only the timestamp of the falling edge will be seen in the PTPSYNCTS
> register, because that of the rising edge had been overwritten. So the
> moral is: don't feed it short pulse inputs.
> Luckily this is not a complete deal breaker, as we can still work with
> 1 Hz square waves. But the problem is that the extts polling period was
> not dimensioned enough for this input signal. If we leave the period at
> half a second, we risk losing timestamps due to jitter in the measuring
> process. So we need to increase it to 4 times per second.
> Also, the very least we can do to inform the user is to deny any other
> flags combination than with PTP_RISING_EDGE and PTP_FALLING_EDGE both
> set.
> Fixes: 747e5eb31d59 ("net: dsa: sja1105: configure the PTP_CLK pin as EXT_TS or PER_OUT")
> Signed-off-by: Vladimir Oltean <>

Acked-by: Richard Cochran <>

Powered by blists - more mailing lists