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Date:   Wed, 13 May 2020 15:39:25 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Oleksij Rempel <o.rempel@...gutronix.de>
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Mark Rutland <mark.rutland@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        linux-kernel@...r.kernel.org,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org,
        Marek Vasut <marex@...x.de>, David Jander <david@...tonic.nl>,
        devicetree@...r.kernel.org
Subject: Re: [PATCH net-next v1] net: phy: tja11xx: add cable-test support

On Wed, May 13, 2020 at 02:34:40PM +0200, Oleksij Rempel wrote:
> Add initial cable testing support.
> This PHY needs only 100usec for this test and it is recommended to run it
> before the link is up. For now, provide at least ethtool support, so it
> can be tested by more developers.
> 
> This patch was tested with TJA1102 PHY with following results:
> - No cable, is detected as open
> - 1m cable, with no connected other end and detected as open
> - a 40m cable (out of spec, max lenght should be 15m) is detected as OK.
> 
> Current patch do not provide polarity test support. This test would
> indicate not proper wire connection, where "+" wire of main phy is
> connected to the "-" wire of the link partner.
> 
> Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
> ---
>  drivers/net/phy/nxp-tja11xx.c | 106 +++++++++++++++++++++++++++++++++-
>  1 file changed, 105 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c
> index ca5f9d4dc57ed..8b743d25002b9 100644
> --- a/drivers/net/phy/nxp-tja11xx.c
> +++ b/drivers/net/phy/nxp-tja11xx.c
> @@ -5,6 +5,7 @@
>   */
>  #include <linux/delay.h>
>  #include <linux/ethtool.h>
> +#include <linux/ethtool_netlink.h>
>  #include <linux/kernel.h>
>  #include <linux/mdio.h>
>  #include <linux/mii.h>
> @@ -26,6 +27,7 @@
>  #define MII_ECTRL_POWER_MODE_NO_CHANGE	(0x0 << 11)
>  #define MII_ECTRL_POWER_MODE_NORMAL	(0x3 << 11)
>  #define MII_ECTRL_POWER_MODE_STANDBY	(0xc << 11)
> +#define MII_ECTRL_CABLE_TEST		BIT(5)
>  #define MII_ECTRL_CONFIG_EN		BIT(2)
>  #define MII_ECTRL_WAKE_REQUEST		BIT(0)
>  
> @@ -55,6 +57,11 @@
>  #define MII_GENSTAT			24
>  #define MII_GENSTAT_PLL_LOCKED		BIT(14)
>  
> +#define MII_EXTSTAT			25
> +#define MII_EXTSTAT_SHORT_DETECT	BIT(8)
> +#define MII_EXTSTAT_OPEN_DETECT		BIT(7)
> +#define MII_EXTSTAT_POLARITY_DETECT	BIT(6)
> +

Do these registers all conform to the standard? Can we pull this code
out into a library which all standards conformant PHY drivers can use?

The code itself looks O.K.

    Andrew

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