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Message-ID: <AM6PR0402MB3607362AAEB1B5B5182F190BFFB30@AM6PR0402MB3607.eurprd04.prod.outlook.com>
Date: Mon, 25 May 2020 15:41:40 +0000
From: Andy Duan <fugang.duan@....com>
To: Andrew Lunn <andrew@...n.ch>
CC: "martin.fuzzey@...wbird.group" <martin.fuzzey@...wbird.group>,
"davem@...emloft.net" <davem@...emloft.net>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"kuba@...nel.org" <kuba@...nel.org>
Subject: RE: [EXT] Re: [PATCH net v2 0/4] net: ethernet: fec: move GPR
reigster offset and bit into DT
From: Andrew Lunn <andrew@...n.ch> Sent: Monday, May 25, 2020 9:55 PM
> On Mon, May 25, 2020 at 03:09:25PM +0800, fugang.duan@....com wrote:
> > From: Fugang Duan <fugang.duan@....com>
> >
> > The commit da722186f654 (net: fec: set GPR bit on suspend by DT
> configuration) set the GPR reigster offset and bit in driver for wol feature.
>
> The cover letter gets committed as the merge commit message. So please
> wrap long longs.
>
> > It bring trouble to enable wol feature on imx6sx/imx6ul/imx7d
> > platforms that have multiple ethernet instances with different GPR bit
> > for stop mode control. So the patch set is to move GPR reigster
>
> register
>
Got it, will correct the typo in v3.
> > offset and bit define into DT, and enable
> > imx6q/imx6dl/imx6sx/imx6ul/imx7d stop mode support.
>
>
> >
> > Currently, below NXP i.MX boards support wol:
> > - imx6q/imx6dl sabresd
> > - imx6sx sabreauto
> > - imx7d sdb
> >
> > imx6q/imx6dl sarebsd board dts file miss the property "fsl,magic-packet;",
> so patch#4 is to add the property for stop mode support.
>
> sabresd?
>
> Andrew
Thanks, I will correct the typo in v3.
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